Semiconductor memory device and system having redundancy cells

ABSTRACT

In one embodiment, the memory device includes a memory cell array, to data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Patent Application No.61/556,597, filed on Nov. 7, 2011, in the US Patent Office and KoreanPatent Nos. 10-2012-0093879 and 10-2012-0093883, filed on Aug. 27, 2012and Aug. 27, 2012, in the Korean Intellectual Property Office, thedisclosures of all of which are incorporated herein in their entirety byreference.

BACKGROUND

The inventive concepts relate to a semiconductor memory device, and moreparticularly, to a semiconductor memory device and/or system havingredundancy cells, and/or methods associated therewith.

A consistent increase in the size of semiconductor memories has caused agradual increase in a defective cell occurrence probability. Accordingto the existing methods of repairing such a defective cell, when adefective cell occurrence probability increases, redundancy resourcesare limited due to the limitation in flexibility of a repair unit. Inaddition, if a group unit of redundancy cells replaced due to anincrease in memory density is constant, the number of replacedredundancy cells increases, causing an increase in a chip size.

SUMMARY

At least one embodiment relates to a memory device.

In one embodiment, the memory device includes a memory cell array, adata line selection circuit and selection control logic. The memory cellarray has at least a first memory cell group and a redundancy memorycell group. The first memory cell group includes a plurality of firstmemory cells associated with a first data line, and the redundancymemory cell group includes a plurality of redundancy memory cellsassociated with a redundancy data line. The selection control logic isconfigured to detect if a defective memory cell in the first memory cellgroup is being accessed, and is configured to control the data lineselection circuit to replace access via the first data line with accessvia the redundancy data line such that a detected defective memory cellin the first memory cell group is replaced with one of the plurality ofredundancy memory cells. The selection control logic includes a storagedevice configured to store address information for defective memorycells. The address information includes row address information andcolumn address information identifying rows and columns in the firstmemory cell group including defective memory cells. The selectioncontrol logic also includes control signal generation logic configuredto generate a control signal for controlling the data line selectioncircuit based on the address information and a received address. Thereceived address identifies at least one memory cell in the cell arraybeing accessed.

In one embodiment, the control signal generation logic includes acomparator configured to compare the address information and thereceived address, and the control signal generation logic is configuredto generate the control signal based on the comparison.

In one embodiment, the comparator includes a row comparator and a columncomparator. The row comparator is configured to compare the row addressinformation with a received row address represented by the receivedaddress. The column comparator is configured to compare the columnaddress information with a received column address represented by thereceived address.

In one embodiment, the row comparator includes a row address memoryunit. The row address memory unit is configured to receive the rowaddress information from the storage device and store the row addressinformation.

In one embodiment, the column comparator includes a column addressmemory unit. The column address memory unit is configured to receive thecolumn address information from the storage device and store the columnaddress information.

In one embodiment, the storage device is a non-volatile memory device,and the row and column address memory units are volatile memory devices.For example, the volatile memory devices may be content addressablememories.

In one embodiment, the comparator is configured to generate a selectionsignal based on the comparison. The selection signal indicates whether adefective memory cell exists and identifies a memory group including thedefective memory cell, and the control signal generation logic isconfigured to generate the control signal based on the selection signal.

In one embodiment, the control signal generation logic further includesa code generator configured to generate the control signal based on theselection signal. For example, the control signal includes a bit forcontrolling operation of each selection unit in the data line selectioncircuit.

In one embodiment, the memory cell array includes first to nth memorycell groups, where n is greater than or equal to 2. Each of the first tonth memory cell groups is associated with first to nth data lines. Here,the data line selection circuit is configured to provide data pathsbetween (i) the redundancy data line and the first to nth data lines and(ii) first to nth input/output nodes.

In one embodiment, the data line selection circuit includes first to nthselection units. Each of the first to nth selection units is associatedwith a respective one of the first to nth input/output nodes. Each ofthe first to nth selection units has a first node associated with arespective one of the first-nth data lines and has a second nodeassociated with one of the redundancy data line and the first to nthdata lines. Each of the first to nth selection units is configured toprovide a data path from one of the first and second nodes to theassociated one of first to nth input/output nodes based on the controlsignal. In one embodiment, each of the first to nth selection unitsincludes a multiplexer. In one embodiment, each of the first to nthinput/output nodes is a DQ pad. In one embodiment, the control signalgeneration logic includes a comparator configured to compare the addressinformation and the received address, and the control signal generationlogic is configured to generate the control signal based on thecomparison.

In one embodiment, the comparator is configured to generate a selectionsignal based on the comparison. The selection signal indicates whether adefective memory cell exists and identifies a one of the first to nthmemory groups including the defective memory cell, and the controlsignal generation logic is configured to generate the control signalbased on the selection signal.

In one embodiment, the control signal generation logic further includesa code generator configured to generate the control signal based on theselection signal. The control signal includes a bit associated with eachof the first to nth selection units, each bit of the control signalindicating which of the first and second nodes of the associated one ofthe first to nth selection units to couple to the associated one of thefirst to nth input/output nodes.

In one embodiment, the second node of the first to (n−1)th selectionunits is associated with the data line for the second to nth memory cellgroups; the second node of the nth selection unit is associated with theredundancy data line; and the control signal generation logic isconfigured to generate a control signal such that if a detecteddefective memory cell is in the mth memory cell group, the first to mthselection units provide a data path including the second node, and the(m+1)th to nth selection units provide a data path including the firstnode.

In one embodiment, the control signal generation logic is configured togenerate the control signal such that the data paths provided by thedata line selection circuit do not include a one of the first to nthdata lines associated with a one of the first to nth memory cell groupsincluding a detected defective memory cell.

In one embodiment, at least one of the first to nth data lines isconnected to a sense amplifier arranged in a lengthwise direction of thememory cell array, and at least one of the first to nth data lines isconnected to a sense amplifier arranged in a widthwise direction of thememory cell array.

In one embodiment, the storage device is configured to store addressinformation such that one of the first to nth memory cell groupsincluding a defective memory cell is replaced by the redundancy memorycell group.

In one embodiment, the storage device is configured to store addressinformation such that a defective memory cell is replaced by a singleredundancy memory cell. In one embodiment, the selection control logicis configured to not replace non-defective memory cells in a columnincluding the defective memory cell such that the non-defective memorycells remain accessible.

In one embodiment, the storage device is configured to store addressinformation such that a column of memory cells including a defectivememory cell are replaced by a column of redundancy memory cells.

In one embodiment, the storage device is configured to store addressinformation such that only a portion of a column of memory cellsincluding a defective memory cell are replaced by a portion of a columnof redundancy memory cells. In one embodiment, the selection controllogic is configured to not replace non-defective memory cells in aremaining portion of the column including the defective memory cell suchthat the non-defective memory cells in the remaining portion remainaccessible.

In one embodiment, the first memory cell group includes at least onecolumn of internal redundancy memory cells for replacing defectivememory cells in the first memory cell group.

In one embodiment, the memory device includes a memory cell array, adata line selection circuit and selection control logic. The memory cellarray has at least a first memory cell group and a redundancy memorycell group. The first memory cell group includes a plurality of firstmemory cells arranged in columns and rows, and the plurality of firstmemory cells are associated with a first data line. The redundancymemory cell group includes a plurality of redundancy memory cellsarranged in columns and rows, and the plurality of redundancy memorycells are associated with a redundancy data line. The selection controllogic is configured to detect if a defective memory cell in the firstmemory group is being accessed, and is configured to control the dataline selection circuit to replace access via the first data line withaccess via the redundancy data line such that a portion of a column ofthe plurality of first memory cells including the detected defectivememory cell in the first group is replaced with a portion of a column ofthe plurality of redundancy memory cells.

In one embodiment, the portion of the column of the plurality of firstmemory cells includes a non-defective memory cell. In one embodiment,the selection control logic is configured to not replace non-defectivememory cells in a remaining portion of the column including thedefective memory cell such that the non-defective memory cells in theremaining portion remain accessible.

In one embodiment, the memory device includes a memory cell array, adata line selection circuit and selection control logic. The memory cellarray has first to nth memory cell groups and a redundancy memory cellgroup, where n is greater than or equal to 2. Each of the first to nthmemory cell groups is associated with first to nth data lines. The firstto nth memory cell groups include first to nth pluralities of memorycells arranged in columns and rows, and the redundancy memory cell groupincludes a plurality of redundancy memory cells arranged in columns androws. The plurality of redundancy memory cells are associated with aredundancy data line. The selection control logic is configured todetect if a defective memory cell in one of the first to nth memorygroups is being accessed, and is configured to control the data lineselection circuit to replace access via one of the first to nth datalines with access via the redundancy data line such that the one of thefirst to nth memory cells groups including the detected defective memorycell is replaced with the redundancy memory cell group.

In one embodiment, the memory device includes a memory cell array, adata line selection circuit and selection control logic. The memory cellarray has at least a first memory cell group and a redundancy memorycell group. The first memory cell group includes a plurality of firstmemory cells arranged in columns and rows, and the plurality of firstmemory cells are associated with a first data line. The redundancymemory cell group includes a plurality of redundancy memory cellsarranged in columns and rows, and the plurality of redundancy memorycells are associated with a redundancy data line. The selection controllogic is configured to detect if a defective memory cell in the firstmemory group is being accessed, and is configured to control the dataline selection circuit to replace access via the first data line withaccess via the redundancy data line such that a detected defectivememory cell in the first group is replaced with one of the plurality ofredundancy memory cells according to a desired replacement scheme. Thedesired replacement scheme is a programmable feature of the selectioncontrol logic.

In one embodiment, the desired replacement scheme causes the selectioncontrol logic to replace one of the first to nth memory cell groupsincluding a defective memory cell with the redundancy memory cell group.

In one embodiment, the desired replacement scheme causes the selectioncontrol logic to replace a defective memory cell with a singleredundancy memory cell.

In one embodiment, the desired replacement scheme causes the selectioncontrol logic to not replace non-defective memory cells in a columnincluding the defective memory cell such that the non-defective memorycells remain accessible.

In one embodiment, the desired replacement scheme causes the selectioncontrol logic to replace a column of memory cells including a defectivememory cell with a column of redundancy memory cells.

In one embodiment, the desired replacement scheme causes the selectioncontrol logic to replace only a portion of a column of memory cellsincluding a defective memory cell with a portion of a column ofredundancy memory cells. In one embodiment, the desired replacementscheme causes the selection control logic to not replace non-defectivememory cells in a remaining portion of the column including thedefective memory cell such that the non-defective memory cells in theremaining portion remain accessible.

In one embodiment, the selection control logic includes a storage deviceconfigured to be programmed with address information for defectivememory cells according to the desired replacement scheme. The addressinformation includes row address information and column addressinformation identifying rows and columns in the first to nth memory cellgroups including defective memory cells. The control signal generationlogic is configured to generate a control signal for controlling thedata line selection circuit based on the address information and areceived address. The received address identifies at least one memorycell in the cell array being accessed.

At least one embodiment relates to system such as a computer system,memory card, electronic device, wireless phone, etc. including thememory device according to one of the example embodiments.

At least one embodiment relates to a method of replacing defectivememory cells.

In one embodiment, the method is applied to a memory cell array havingat least a first memory cell group and a redundancy memory cell group,the first memory cell group including a plurality of first memory cellsassociated with a first data line, and the redundancy memory cell groupincluding a plurality of redundancy memory cells associated with aredundancy data line. The method includes detecting if a defectivememory cell in the first memory cell group is being accessed, andcontrolling a data line selection circuit to replace access via thefirst data line with access via the redundancy data line such that adetected defective memory cell in the first memory cell group isreplaced with one of the plurality of redundancy memory cells. Thecontrolling includes storing, in a storage device, address informationfor defective memory cells. The address information includes row addressinformation and column address information identifying rows and columnsin the first memory cell group including defective memory cells. Thecontrolling also includes generating a control signal for controllingthe data line selection circuit based on the address information and areceived address. The received address identifies at least one memorycell in the cell array being accessed.

In another embodiment, the method applies to a memory cell array havingat least a first memory cell group and a redundancy memory cell group,the first memory cell group including a plurality of first memory cellsarranged in columns and rows, and the plurality of first memory cellsbeing associated with a first data line, and the redundancy memory cellgroup including a plurality of redundancy memory cells arranged incolumns and rows, and the plurality of redundancy memory cells beingassociated with a redundancy data line. The method includes detecting ifa defective memory cell in the first memory group is being accessed, andcontrolling, by a selection control logic, a data line selection circuitto replace access via the first data line with access via the redundancydata line such that a portion of a column of the plurality of firstmemory cells including the detected defective memory cell in the firstgroup is replaced with a portion of a column of the plurality ofredundancy memory cells.

In one embodiment, the method applies to a memory cell array havingfirst to nth memory cell groups and a redundancy memory cell group,where n is greater than or equal to 2. Each of the first to nth memorycell groups is associated with first to nth data lines. The first to nthmemory cell groups includes first to nth pluralities of memory cellsarranged in columns and rows, and the redundancy memory cell groupincludes a plurality of redundancy memory cells arranged in columns androws. The plurality of redundancy memory cells is associated with aredundancy data line. The method includes detecting if a defectivememory cell in one of the first to nth memory groups is being accessed,and controlling, by a selection control logic, a data line selectioncircuit to replace access via the first data line with access via theredundancy data line such that the one of the first to nth memory cellsgroups including the detected defective memory cell is replaced with theredundancy memory cell group.

In one embodiment, the method applies to a memory cell array having atleast a first memory cell group and a redundancy memory cell group, thefirst memory cell group including a plurality of first memory cellsarranged in columns and rows, and the plurality of first memory cellsbeing associated with a first data line, the redundancy memory cellgroup including a plurality of redundancy memory cells arranged incolumns and rows, and the plurality of redundancy memory cells beingassociated with a redundancy data line. The method includes detecting ifa defective memory cell in the first memory group is being accessed, andcontrolling, by a selection control logic, a data line selection circuitto replace access via the first data line with access via the redundancydata line such that a detected defective memory cell in the first groupis replaced with one of the plurality of redundancy memory cellsaccording to a desired replacement scheme. The desired replacementscheme is a programmable feature of the selection control logic.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the inventive concepts will be more clearlyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings in which:

FIG. 1 is a block diagram of a semiconductor memory device according toan embodiment of the inventive concepts;

FIG. 2 is a circuit diagram of a first memory cell group in thesemiconductor memory device of FIG. 1;

FIGS. 3A to 3F are diagrams for describing methods of replacing adefective cell with a redundancy cell;

FIG. 4 is a block diagram of a memory array according to anotherembodiment of the inventive concepts.

FIG. 5 is a block diagram of a semiconductor memory device according toanother embodiment illustrating the replacement control architecture indetail.

FIGS. 6A to 6D are block diagrams of a semiconductor memory device fordescribing the data line selection circuit in greater detail.

FIGS. 7A to 7C are a block diagram and tables for describing generationof a control signal for controlling a data line selection block;

FIG. 7D shows an example of data line replacement;

FIG. 7E is a block diagram illustrating an example in which ademultiplexer is installed for a redundancy memory cell group;

FIGS. 7F and 7G are block diagrams of a semiconductor memory deviceaccording to another embodiment of the inventive concepts;

FIG. 7H is a block diagram of an example in which the design of thesemiconductor memory device of FIGS. 7F and 7G is modified;

FIG. 8 is a circuit diagram illustrating a repair operation incorrespondence with various data width options, according to anembodiment of the inventive concepts;

FIGS. 9A to 9C are circuit diagrams for describing operations of asemiconductor memory device of FIG. 8;

FIG. 10 is a circuit diagram for describing an operation of asemiconductor memory device in an X16 data width option of operation;

FIG. 11 is a block diagram of a semiconductor memory device according toanother embodiment of the inventive concepts;

FIG. 12 is a circuit diagram of the semiconductor memory device of FIG.11;

FIGS. 13A to 13C are circuit diagrams for describing operations of thesemiconductor memory device of FIG. 12 in X8 and X4 data width options;

FIG. 14 is a block diagram for describing an operation of thesemiconductor memory device of FIG. 12 in the X16 data width option;

FIG. 15 is a block diagram of a semiconductor memory device according toanother embodiment of the inventive concepts;

FIGS. 16, 17A, and 17B are circuit diagrams for describing operations ofthe semiconductor memory device of FIG. 15;

FIG. 18 is a block diagram of a semiconductor memory device according toanother embodiment of the inventive concepts;

FIGS. 19A to 19C are circuit diagrams for describing operations of thesemiconductor memory device of FIG. 18;

FIG. 20 is a block diagram of a semiconductor memory device according toanother embodiment of the inventive concepts;

FIGS. 21A to 21D are circuit diagrams and block diagrams for describingthe semiconductor memory device of FIG. 20;

FIG. 22 is a detailed block diagram of a semiconductor memory deviceaccording to an embodiment of the inventive concepts;

FIG. 23 is a block diagram of a memory system according to an embodimentof the inventive concepts;

FIG. 24 is a block diagram of a semiconductor storage system accordingto an embodiment of the inventive concepts;

FIG. 25 is a block diagram of a network system according to anembodiment of the inventive concepts; and

FIG. 26 is a block diagram of another memory system to which asemiconductor memory device according to an embodiment of the inventiveconcepts is applied.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Example embodiments will now be described more fully with reference tothe accompanying drawings. However, example embodiments may be embodiedin many different forms and should not be construed as being limited tothe example embodiments set forth herein. Example embodiments areprovided so that this disclosure will be thorough, and will fully conveythe scope to those who are skilled in the art. In some exampleembodiments, well-known processes, well-known device structures, andwell-known technologies are not described in detail to avoid the unclearinterpretation of the example embodiments. Throughout the specification,like reference numerals in the drawings denote like elements.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “coupled to” another element or layer, itmay be directly on, connected or coupled to the other element or layer,or intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there may be nointervening elements or layers present. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, third,etc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsmay be only used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the example embodiments.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms may be intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the example term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting. As usedherein, the singular forms “a”, “an” and “the” may be intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the figures.For example, two figures shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art. It will be further understood that terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe context of the relevant art and will not be interpreted in anidealized or overly formal sense unless expressly so defined herein.

Referring to FIG. 1, the semiconductor memory device 100 may include amemory cell array 110, a column decoder 120, a row decoder 130, anaddress controller 140, and replacement control architecture 150.

The semiconductor memory device 100 may be a dynamic random accessmemory (DRAM) device. However, the semiconductor memory device 100 isnot limited thereto and may include a plurality of memories of differenttypes, such as a random-access memory (RAM), a read only memory (ROM), asynchronous dynamic random access memory (SDRAM), a NAND flash memory, aNOR flash memory, a Phase-Change Random Access Memory (PRAM), a MagneticRandom Access memory (MRAM), a Resistive Random Access Memory (ReRAM),and a Ferroelectric Random Access Memory (FRAM), which may be providedas internal semiconductor integrated circuits in computers and otherelectronic devices.

The memory cell array 110 may include a plurality of memory cell groups.For example, the memory cell array 110 may include a first memory cellgroup 111, a second memory cell group 112, a third memory cell group113, and a fourth memory cell group 114. The memory cell array 110 mayfurther include a redundancy cell group 115.

A fault may occur in at least one of memory cells included in the firstto fourth memory cell groups 111, 112, 113, and 114. In thespecification, a defective cell may be referred to as a single bit or aweak cell. A weak cell in the first to fourth memory cell groups 111,112, 113, and 114 may be replaced with a redundancy cell included in theredundancy cell group 115 by the replacement control architecture 150.

Each of the first to fourth memory cell groups 111, 112, 113, and 114may be defined in various ways. For example, the memory cell array 110may include a plurality of memory banks or memory blocks, wherein eachof the first to fourth memory cell groups 111, 112, 113, and 114 may bedefined as a memory bank or a memory block. Alternatively, each of thefirst to fourth memory cell groups 111, 112, 113, and 114 may be definedas an area for inputting and outputting data through a different dataline. In detail, memory cells included in each of the first to fourthmemory cell groups 111, 112, 113, and 114 may be connected to globaldata lines through bit lines (not shown) and local data lines (notshown). For example, data in memory cells included in the first memorycell group 111 may be transferred through first to fourth global datalines GDL[1,1], GDL[1,2], GDL[1,3], and GDL[1,4] in a first group.Likewise, data in memory cells included in the second memory cell group112 may be transferred through first to fourth global data linesGDL[2,1], GDL[2,2], GDL[2,3], and GDL[2,4] in a second group, data inmemory cells included in the third memory cell group 113 may betransferred through first to fourth global data lines GDL[3,1],GDL[3,2], GDL[3,3], and GDL[3,4] in a third group, and data in memorycells included in the fourth memory cell group 114 may be transferredthrough first to fourth global data lines GDL[4,1], GDL[4,2], GDL[4,3],and GDL[4,4] in a fourth group.

Data in redundancy cells included in the redundancy cell group 115 mayalso be transferred through bit lines (e.g., redundancy bit lines (notshown)), local data lines (e.g., redundancy data lines (not shown)), andglobal data lines (e.g., first to fourth redundancy global data linesRGDL[1], RGDL[2], RGDL[3], and RGDL[4]). The same row and correspondingcolumn as one of the accessed memory cell groups is accessed via theredundancy global bit lines RGBL. FIG. 1 shows an example in which thefirst to fourth redundancy global data lines RGDL[1], RGDL[2], RGDL[3],and RGDL[4] are arranged to correspond to the number of global datalines corresponding to each memory cell group 111, 112, 113, or 114.However, the number of global data lines and the number of redundancyglobal data lines are only illustrative, and the number of global datalines may also be changed in correspondence with the number of columnsbelonging to each memory cell group 111, 112, 113, or 114. For example,the first memory cell group 111 may be connected to 1, 2, 8, or moreglobal data lines. Accordingly, the redundancy cell group 115 may beconnected to 1, 2, 8, or more redundancy global data lines.

FIG. 2 is a circuit diagram of the first memory cell group 111 in thesemiconductor memory device 100 of FIG. 1. The second to fourth memorycell groups 112, 113, and 114 may be configured in the same or similarmanner to the first memory cell group 111 shown in FIG. 2. Theredundancy cell group 115 may also be configured in the same or similarmanner to the first memory cell group 111 shown in FIG. 2.

Referring to FIG. 2, the first memory cell group 111 may include memorycells connected to first to pth word lines WL[1], WL[2], WL[3] . . . ,WL[p] and first to qth bit lines BL[1], BL[2], BL[3] . . . , BL[q].Writing to or reading from the first memory cell group 111 may beperformed using a general semiconductor memory device write or readmethod. For example, the row decoder 130 decodes a row address RA inputfrom the address controller 140. The decoded row address RA may enablethe first to pth word lines WL[1] to WL[p] in the memory cell array 110.The column decoder 120 decodes a column address CA input from theaddress controller 140. The decoded column address CA may enable aselection operation of the first to qth bit lines BL[1] to BL[q] in thememory cell array 110 through a column selection line.

Data may be written or read by enabling the first to pth word linesWL[1] to WL[p] and the first to qth bit lines BL[1] to BL[q]. Dataapplied to the first to qth bit lines BL[1] to BL[q] is transferred tofirst to qth local data lines LDL[1], LDL[2], LDL[3] . . . , LDL[q] inresponse to a column selection operation, and data amplified by first toqth local sense amplifiers LSA[1], LSA[2], LSA[3] . . . , LSA[q] istransferred to first to qth global data lines GDL[1], GDL[2], GDL[3] . .. , GDL[q].

Data lines for transferring data in the redundancy cell group 115 mayalso have the local data line and global data line structure. Referringback to FIG. 1, data in the redundancy cell group 115 may be transferredthrough the first to fourth redundancy global data lines RGDL[1],RGDL[2], RGDL[3], and RGDL[4] over bit lines and redundancy local datalines connected to the redundancy cells. The local data lines connectedto the first memory cell group 111 may be separated from the redundancylocal data lines connected to the redundancy cell group 115, and thefirst to fourth global data lines GDL[1,1] to GDL[1,4] in the firstgroup that are connected to the first memory cell group 111 may beseparated from the first to fourth redundancy global data lines RGDL[1]to RGDL[4] connected to the redundancy cell group 115. According to anembodiment of the inventive concepts, a repair unit may be flexiblyadjusted in relation to a range between single cell repair and cellgroup repair when a weak cell occurs, instead of repair of the entirebit lines or the entire word lines.

For example, as shown in FIG. 1, when a weak cell Weak Cell[1] occurs atan intersection of a word line WL[i] and a bit line BL[j], the weak cellWeak Cell[1] may be replaced with a redundancy cell Redundancy Cell[1].That is, data to be written to or read from the weak cell Weak Cell[1]may be written to or read from the redundancy cell Redundancy Cell[1].According to an embodiment of the inventive concepts, a repair operationof a weak cell is performed by arranging separate local data lines andglobal local data lines in correspondence with the redundancy cell group115 and replacing a data line connected to the weak cell with a dataline connected to a redundancy cell. For example, repair may beperformed by replacement of a global data line. By doing so, only oneredundancy cell group 115 may be arranged in correspondence with thefirst to fourth memory cell groups 111, 112, 113, and 114, and a bitunit repair or a group unit repair may be performed by using theredundancy cell group 115.

FIGS. 3A to 3F are diagrams for describing methods of replacing the WeakCell[1] with the Redundancy Cell[1]. For convenience of description,only a case where a weak cell occurs in the first memory cell group 111is described. The replacement control architecture 150 for effecting thereplacement schemes of FIGS. 3A-3F will be described in detail after thedescription of the replacement schemes of FIGS. 3A-3F.

FIG. 3A is a diagram for describing replacement between memory cellgroups. For example, when a weak cell CELL[1, 3] occurs in the firstmemory cell group 111, the first memory cell group 111 may be replacedwith the redundancy cell group 115. That is, when the weak cell CELL[1,3] occurs in the first memory cell group 111, an address with respect tothe first memory cell group 111 including the weak cell CELL[1, 3] maybe processed by determining the address with respect to the first memorycell group 111 as an address with respect to the redundancy cell group115. As will be appreciated, in this replacement scheme, normal ornon-defective memory cells may be replaced along with the defectivememory cell by redundancy memory cells.

FIG. 3B is a diagram for describing replacement between bit lines. Forexample, when a fault occurs in the cell CELL[1, 3] connected to thethird bit line BL[3] in the first memory cell group 111, cells connectedto the third bit line BL[3] may be replaced with cells connected to one(e.g., a third redundancy bit line RBL[3]) of first to pth redundancybit lines RBL[1] to RBL[q] connected to the redundancy cell group 115.That is, a column address CA with respect to the third bit line RBL[3]may be processed by determining the column address CA with respect tothe third bit line RBL[3] as a column address CA with respect to one ofthe first to pth bit lines RBL[1] to RBL[q] connected to the redundancycell group 115. As will be appreciated, in this replacement scheme,normal or non-defective memory cells may be replaced along with thedefective memory cell by redundancy memory cells.

FIG. 3C is a diagram for describing replacement between portions of bitlines (e.g., segments of bit lines). A single bit line may be dividedinto two or more segments, each segment being connected to at least onememory cell. For example, the weak cell CELL[1, 3] occurs in a segmentof cells connected to the third bit line RBL[3] in the first memory cellgroup 111, the segment of the cells connected to the third bit lineRBL[3] that includes the weak cell CELL[1, 3] may be replaced with asegment of cells connected to one of the first to pth redundancy bitlines RBL[1] to RBL[q] connected to the redundancy cell group 115. Inaddition, when the weak cell CELL[1, 3] occurs in a specific segment ofthe third bit line RBL[3] in the first memory cell group 111, thesegment in which the weak cell CELL[1, 3] has occurred may be replacedwith a corresponding segment connected to one of the first to pth bitlines RBL[1] to RBL[q] connected to the redundancy cell group 115. Thatis, a column address CA with respect to the third bit line RBL[3] may beprocessed by determining the column address CA with respect to the thirdbit line RBL[3] as a column address CA with respect to one of the firstto pth bit lines RBL[1] to RBL[q] connected to the redundancy cell group115 and determining at least some bits of a row address RA as word linesconnected to the redundancy cell group 115. For example, when all bitsof the row address RA are used for comparison, a segment may include onememory cell, and when the most significant bit (MSB) is ignored (don'tcare), a segment may include memory cells corresponding to half ofmemory cells connected to a single bit line. As will be appreciated, inthis replacement scheme, normal or non-defective memory cells may bereplaced along with the defective memory cell by redundancy memorycells. As will be further appreciated, the memory cells of the columnnot in the segment, may be accessed (read from and written to) in thenormal manner.

FIG. 3D is a diagram for describing replacement between memory cells.For example, when the weak cell CELL[1, 3] occurs in the first memorycell group 111, the weak cell CELL[1, 3] may be replaced with aredundancy cell. That is, repair may be performed in a single memorycell unit by determining and processing a column address CA and a rowaddress RA with respect to the weak cell CELL[1, 3] as a column addressCA and a row address RA with respect to a redundancy cell. As will befurther appreciated, the memory cells of the column not selected forreplacement, may be accessed (read from and written to) in the normalmanner.

According to another embodiment of the inventive concepts, in thesemiconductor memory device 100, an internal redundancy memory cellgroup for internally performing repair in each of the first to fourthmemory cell groups 111, 112, 113, and 114 may be included in the firstto fourth memory cell groups 111, 112, 113, and 114, and the separateredundancy memory cell group 115 may be arranged for repair with respectto the first to fourth memory cell groups 111, 112, 113, and 114. Forexample, as shown in FIG. 3E, the first memory cell group 111 mayinclude an internal redundancy memory cell group 111_1 therein, andfirst to rth redundancy bit lines IRBL[1] to IRBL[r] may be arranged incorrespondence with the internal redundancy memory cell group 111_1.Accordingly, weak cells in the first memory cell group 111 may be firstrepaired by using the internal redundancy memory cell group 111_1included in the first memory cell group 111, and when additional weakcells occur, repair using the redundancy memory cell group 115 may beperformed.

Similarly, as shown in FIG. 3F, the first memory cell group 111 mayinclude an internal redundancy memory cell group 111_2 therein, and theinternal redundancy memory cell group 111_2 may include redundancy cellsconnected to a single redundancy bit line IRBL[r].

The repair operations of a weak cell that are shown in FIGS. 3E and 3Fmay be performed in various ways. For example, in FIG. 3E, the first torth redundancy bit lines IRBL[1] to IRBL[r] in the internal redundancymemory cell group 111_1 may be connected to the same data lines (e.g.,local data lines) as the first to pth bit lines BL[1] to BL[q] in thefirst memory cell group 111, and repair may be performed by replacementin a group unit of one or more bit lines. In addition, the redundancymemory cell group 115 may be connected to separate data lines (e.g.,local data lines and global data lines), and repair may be performed byreplacement in a data line (e.g., global data line) unit with the firstmemory cell group 111. However, this is only illustrative, and separatedata lines may be arranged in correspondence with the internalredundancy memory cell group 111_1, and repair may be performed byreplacement in a data line unit.

With respect to the above discussed replacement schemes, it will beunderstood that the example embodiments are not limited to a memory cellarray having four memory cell groups as shown in FIG. 1. Instead, moreor less than four memory cell groups may be included in the memory cellarray.

FIG. 4 is a block diagram of a memory array according to anotherembodiment of the inventive concepts, which may be combined with any ofthe embodiments described herein. As shown in FIG. 4, a memory cellarray 310 has a plurality of memory cell groups, e.g., first to fourthmemory cell groups 311 to 314, and a redundancy memory cell group 315.

Referring to FIG. 4, each of the first to fourth memory cell groups 311to 314 may be connected to at least one global data line, and forexample, the first memory cell group 311 is connected to first andsecond global data lines GDL1 and GDL2, the second memory cell group 312is connected to third and fourth global data lines GDL3 and GDL4, thethird memory cell group 313 is connected to fifth and sixth global datalines GDL5 and GDL6, and the fourth memory cell group 314 is connectedto seventh and eighth global data lines GDL7 and GDL8. The first toeighth global data lines GDL1 to GDL8 are connected to local data lines(not shown) via local sense amplifiers (LSA). A plurality of horizontalLSAs (H-LSAs) 316 may be horizontally arranged in a lengthwise directionof the memory cell array 310 (e.g., a width direction in FIG. 4), andthe first to eighth global data lines GDL1 to GDL8 may be connected tothe plurality of H-LSAs 316.

The redundancy memory cell group 315 may be connected to at least oneredundancy global data line, and for example, FIG. 4 shows that first toeighth redundancy global data lines RGDL1 to RGDL8 are connected to theredundancy memory cell group 315. According to the current embodiment,redundancy local data lines and redundancy global data lines may bearranged in correspondence with the redundancy memory cell group 315,and accordingly, LSAs corresponding to the first to eighth redundancyglobal data lines RGDLI to RGDL8 may be arranged.

Since the redundancy memory cell group 315 has a smaller area than theother memory cell groups 311 to 314, an area for arranging the LSAs maybe limited. Therefore, at least one vertical LSA (V-LSA) 317 may befurther arranged in a width-wise direction of the memory cell array 310(e.g., a vertical direction in FIG. 4) in addition to the H-LSA 316 incorrespondence with the redundancy memory cell group 315. Accordingly, aspace overhead for arranging the LSAs may be minimized.

FIG. 5 is a block diagram of a semiconductor memory device according toanother embodiment that illustrates the replacement control architecturein detail.

Referring to FIG. 5, the semiconductor memory device 200 may include amemory cell array 210, a column decoder 220, a row decoder 230, anaddress controller 240, and replacement control architecture 250. Othercomponents that may be included in the semiconductor memory device 200are not shown.

The memory cell array 210 may be configured in the same or similarmanner to the memory cell array 110 shown in FIG. 1. For example, thememory cell array 210 may include n memory cell groups 211 and mayfurther include a redundancy memory cell group 215 for repairing weakcells occurring in the n memory cell groups 211. Here, n may be one orgreater than one (e.g., 4, 8, 16, 32, 64 . . . ).

The address controller 240 receives an address Addr from the outside andoutputs a row address RA and a column address CA based on the receivedaddress Addr. The row decoder 230 decodes the row address RA to activatea word line of the memory cell array 210. The column decoder 220 decodesthe column address CA to connect data lines of the memory cell groups211 and the redundancy memory cell group 215 to respective global datalines and redundancy global data lines.

The replacement control architecture 250 includes a data line selectioncircuit 260 and selection control logic 270. The data line selectioncircuit 260 provides data paths between (1) global data lines andredundancy global data lines and (2) input/output nodes of the memorydevice. The input/output nodes DQ may be well-known input/output padsDQ0 . . . DQm as shown in FIG. 5. Here, m may be one or greater than one(e.g., 2, 4, 8, 16, 32, 64, etc.). Also, m may be equal to or differentfrom n. Example embodiments of the data line selection circuit 260 willbe described in greater detail below.

The selection control logic 270 includes a non-volatile memory 272 andcontrol signal generation logic 280. The non-volatile memory 272 storesaddress information for defective cells in the memory array 210 and modeinformation. The mode information indicates the operating mode of thememory device 200 such as the data width (X8, X4 even, X4 odd, etc.).The address information includes row address information and columnaddress information identifying rows and columns in the memory cellgroups 211 including defective memory cells. For example, for singledefective cell replacement as shown in FIG. 3D, the row and columnaddress of the defective memory cell may be stored. For the partialcolumn replacement scheme shown in FIG. 3C, bits of the row address maybe dropped from the stored row address to expand the number of rowsbeing addressed. For example, dropping the most significant row addressbit results in half the column including the defective memory cell beingdesignated. For column replacement as shown in FIG. 3B, “don't care” rowaddress would be stored. And, for group replacement, the columns of thegroup, and “don't care” row addresses would be stored. Accordingly, byprogramming the non-volatile memory with address information, thereplacement scheme is programmable, and may be flexibly changed. Forinstance, single cell replacement may be used for one memory cell group,but partial column replacement used with another memory cell group.While the nonvolatile memory 260 is shown as part of the selectioncontrol logic 270, the nonvolatile memory 260 may be outside thesemiconductor memory device 200 (e.g., a module board on which thesemiconductor memory device 200 is mounted). Also, the nonvolatilememory 260 may include nonvolatile storage devices, such as a fuse arrayand an anti-fuse array.

As shown in FIG. 5, the control signal generation logic 280 includes acomparator 282 and a code generator 284. The comparator 282 includes arow comparator 286 and a column comparator 288. The row comparator 286includes a row address content addressable memory CAM_R, which may beone or more registers. During, for example start-up of the memorydevice, the non-volatile memory 272 loads the row address informationFAIL_RA into the row address content addressable memory CAM_R. The rowcomparator 286 compares the row address from the address controller 240with the row address information to determine whether the addressed rowfrom the address controller 240 is included in the row addressinformation. The row comparator 286 enables operation of the columncomparator 288 if a positive determined is made.

The column comparator 288 includes a column address content addressablememory CAM_C, which may be one or more registers. During, for examplestart-up of the memory device, the non-volatile memory 272 loads thecolumn address information FAIL_CA into the column address contentaddressable memory CAM_C. The non-volatile memory 272 also loads themode information into the column address content addressable memoryCAM_C. If the row comparator 286 makes a positive determination, thecolumn comparator 288 compares the column address from the addresscontroller 240 with the column address information to determine whetherthe addressed column from the address controller 240 is included in thecolumn address information. If a positive determination is made, thecolumn comparator 288 generates a selection signal SEL associatedtherewith. The selection signal and its generation will be described ingreater detail below after the description of the data line selectioncircuit 260. The control code generator 284 generates the control signalor code based on the selection signal. The control code generator 284will be described in greater detail below after the description of thedata line selection circuit 260.

The data line selection circuit 260 will now be described in greaterdetail with respect to FIGS. 6A-6D.

Referring to FIG. 6A, the semiconductor memory device 200 will bedescribed as having the memory cell array 210 including first to eighthmemory cell groups 211_1 to 211_8 for the purposes of explanation only.It will be understood that the is description equally applies to lessthan eight memory cell groups (e.g., 4) and greater than eight memorycell groups (e.g., 16). The memory cell array 210 further includes theredundancy memory cell group 215 for replacing defective cells occurringin the first to eighth memory cell groups 211_1 to 211_8. Also, FIGS.6A-6D show an alternative where the data line selection circuit 260 maybe included in the column decoder 220, but is still considered part ofthe selection control logic 270. Although the column decoder 220includes the data line selection circuit 260 in FIG. 6A, the data lineselection circuit 260 may be arranged outside the column decoder 220.Hereinafter, repeated descriptions will be omitted.

The semiconductor memory device 200 performs repair on the basis of adata line selection operation in the data line selection circuit 260.The data line selection circuit 260 is connected to global data lines ofthe first to eighth memory cell groups 211_1 to 211_8 and redundancyglobal data lines of the redundancy memory cell group 215 and inputs andoutputs via first to eighth input/output nodes DQ0 to DQ7. For example,if data to be accessed is stored in normal cells, the data lineselection circuit 260 normally outputs data in the first to eighthmemory cell groups 211_1 to 211_8, otherwise if data in a defective cellis accessed, the data line selection circuit 260 controls data in theredundancy memory cell group 215 to be output instead of the data in thedefective cell.

The data line selection operation described above may be performed onthe basis of the control signal CS, which will be described in greaterdetail below.

An example of the data line selection operation in the semiconductormemory device 200 will now be described. It is assumed in thedescription of the current embodiment that a selection operation ofglobal data lines is performed.

If data stored in normal cells is accessed, data in the first to eighthmemory cell groups 211_1 to 211_8 is output to first to eighthinput/output nodes DQ0 to DQ7 through the data line selection circuit260. Otherwise, if a defective cell in, for example, the third memorycell group 211_3 is accessed, the data line selection circuit 260performs a selection operation of the global data lines and theredundancy global data lines, for example, outputs data in the first andsecond memory cell groups 211_1 and 211_2 at the first and secondinput/output nodes DQ0 and DQ1 and outputs data in the fourth to eighthmemory cell group 211_4 to 211_8 and the redundancy memory cell group215 at the third to eighth input/output nodes DQ2 to DQ7, respectively.

FIG. 6B is a block diagram of an example of the data line selectioncircuit 260 of FIG. 6A. As shown in FIG. 6B, the data line selectioncircuit 260 may include first to eighth selection units 430_1 to 430_8corresponding to the memory cell groups 211 to 215.

A shifting operation of the global data lines is performed according toa selection operation of the first to eighth selection units 430_1 to430_8. For example, in a normal operation, data transferred through theglobal data lines of the fourth memory cell group 211_4 is output at thefourth input/output node DQ3 through the fourth selection unit 430_4.During a data line shifting operation for repairing a defective memorycell, data transferred through the global data lines of the fourthmemory cell group 211_4 is output at the third input/output node DQ2through the third selection unit 430_3 assuming the defective cell isnot in the fourth memory cell group 211_4. In addition, a data output ofa defective cell is blocked, and instead, data in the redundancy memorycell group 215 is output at the eighth input/output node DQ7 through theredundancy global data lines and the eighth selection unit 430_8. On thebasis of the shifting operation, even if any cell in any one of thefirst to eighth selection units 430_1 to 430_8 is defective, repair maybe performed by the single redundancy memory cell group 215.

The recent specifications of semiconductor memory devices require thatinput and output data is output through only specific input and outputpins according to a separately set data width option. For example, in acase of a semiconductor memory device having 16 input and output pins,data is input and output through the 16 input and output pins if an X16data width option (or X16 data width mode) is set, and data is input andoutput through only 8 input and output pins if an X8 data width optionis set. Similarly, if an X4 data width option is set, data is input andoutput through only 4 input and output pins.

If the X8 data width option is set, a memory is selected by a desired(or, alternatively, a predetermined) number of row and column addresses,and for example, a memory may be selected in response to first tothirteenth row addresses RA01 to RA13 and first to tenth columnaddresses CA01 to CA10. Otherwise if the X16 data width option is set,the thirteenth row address RA13 is ignored (don't care), andaccordingly, double data compared to the X8 option may be input andoutput. Otherwise if the X4 data width option is set, an eleventh columnaddress CA11 is further used, and accordingly, half the amount of datacompared to the X8 data width option may be input and output.

In the example shown in FIG. 6B, since each of the first to eighthselection units 430_1 to 430_8 selects global data lines according to a2:1 selection structure, a repair operation may be performed in a datawidth mode for outputting all of first to eighth data to DQ0 to DQ7.

FIG. 6C is a block diagram of another example of the data line selectioncircuit 260 of FIG. 6A. FIG. 6C shows an example in which repair by adata line selection operation corresponding to various data widthoptions is performed, and as shown in FIG. 6C, the data line selectioncircuit 260 may include first to fourth selection units 430_1 to 430_4corresponding to first to fourth memory cell groups 211_1 to 211_4 andredundancy memory cell group 215.

Each of the first to fourth selection units 431 to 434 may be connectedto at least two memory cell groups (including the redundancy memory cellgroup 215). For example, each of the first and second selection units431 and 432 may be connected to global data lines of three memory cellgroups, the third selection unit 433 may be connected to global datalines of two memory cell groups and the redundancy global data lines,and the fourth selection unit 434 may be connected to global data linesof one memory cell group and the redundancy global data lines. However,this is only illustrative, and each of the first to fourth selectionunits 431 to 434 may be implemented to have a same selection circuitstructure.

As a simple example, when a defective cell in the third memory cellgroup 211_3 is accessed in an option for inputting and outputting firstand third data at DQ0 and DQ2, data in the redundancy memory cell group215 is provided as third data at DQ2 through the third selection unit433, and data in the first memory cell group 211_1 is provided as firstdata at DQ0 through the first selection unit 431. In addition, when adefective cell in the second memory cell group 211_2 is accessed in anoption for inputting and outputting second and fourth data at DQ1 andDQ3, data in the redundancy memory cell group 215 is provided as fourthdata at DQ3 through the fourth selection unit 434, and data in thefourth memory cell group 2114 is provided as second data at DQ1 throughthe second selection unit 432.

In addition, in a case of an option for inputting and outputting firstand fourth data at DQ0 and DQ3, a repair operation may be performed byperforming a shifting operation using the same method as in theconnection structure of FIG. 6B.

FIG. 6D is a block diagram of an example of a selection unit shown inFIG. 6C or FIG. 6B. Although FIG. 6D shows an example of the firstselection unit 430_1 for convenience of description, the other selectionunits may also be implemented in the same or similar manner to the firstselection unit 430_1.

As shown in FIG. 6D, the first selection unit 430_1 may include at leastone n:1 multiplexer (MUX). When data in each memory cell group istransferred through eight global data lines, the first selection unit430_1 may include eight MUXs. In addition, the MUXs may be implementedaccording to the number of global data line connections, and forexample, 3:1 MUXs may be used when one of three data transferred throughglobal data lines are selected as in FIG. 6C. As another example, 2:1MUXs may be used when one of two data transferred through global datalines are selected as in FIG. 6B. According to the current embodiment,since various connection structures of global data lines and redundancyglobal data lines may be achieved, the number of MUXs included in asingle selection unit may be variable, and other types of MUXs besidesthe 3:1 and 2:1 MUXs may be used.

In the structure of FIG. 6D, each MUX, for example, during a writeoperation may receive three data and selectively output any one of thethree data. For example, data may be transferred through any one globaldata line according to a selected column selection line from among theglobal data lines connected to a memory cell group. When a first columnselection line CSL0 is selected, data is input to a first MUX 431_1through first global data lines of three memory cell groups, and thefirst MUX 431_1 outputs any one of the three data as first data DQ0.Similarly, when a fifth column selection line CSL4 is selected, data isinput to a fifth MUX 431_5 through fifth global data lines of the threememory cell groups, and the fifth MUX 431_5 outputs any one of the threedata as first data DQ0.

Furthermore, it will be understood that the MUXs create data pathsbetween a connection node and one of a plurality of selection nodes. Inthe example of FIG. 6D, the connection node is connected with theinput/output node DQ0, and the selection nodes are connected to globaldata lines and/or redundancy data line. Accordingly, regardless of theaccess mode (reading or writing), the MUX creates a data path to theselected global data line.

FIGS. 7A to 7C are a block diagram and tables for describing generationof a control signal for controlling the data line selection circuit 260.

FIG. 7A illustrates an embodiment of the memory device 200 the same asFIG. 1 and FIG. 6B, except that the redundancy memory cell group 215 isdisposed next to first memory cell group 211_1 instead of the nth memory(e.g., eighth) memory cell group. Accordingly, the data line selectioncircuit 260 may include a plurality of selection units, e.g., the firstto eighth selection units 430_1 to 430_8 as in FIG. 6B, for switchingdata lines (e.g., global data lines) connected to a plurality of memorycell groups, e.g., the first to eighth memory cell groups 211_1 to211_8, and the redundancy memory cell group 215, except that the firstselection unit 430_1 is connected to the global data lines for theredundancy memory cell group 215 and the first memory cell group 211_1,the second selection unit 430_2 is connected to the global data linesfor the first and second memory cell groups 211_1 and 211_2, . . . , andthe eighth selection unit is connected to the global data lines for theseventh and eighth memory cell groups 211_7 and 211_8.

The control code generator 284, in the selection control logic 270, forcontrolling the first to eighth selection units 430_1 to 430_8 is alsoshown. As shown in FIG. 5 and reshown in FIG. 7A, the control codegenerator 284 may receive the selection signal SEL and generate controlcodes in response thereto.

If an address Addr from the outside is not of a defective cell, thefirst to eighth selection units 430_1 to 430_8 normally output datawithout a shifting operation of data lines. Otherwise, if the addressAddr from the outside is of a defective cell, data is blocked from beingoutput through a data line connected to the defective cell by a shiftingoperation of data lines, and instead, the data is output through a dataline connected to a redundancy cell.

FIGS. 7B and 7C show examples of the selection signal SEL and thecontrol code or control signal CS, and particularly, examples in whichthe control code is implemented by a thermometer code, for the data lineselection circuit embodiment of FIG. 7A.

The control code generator 284 may store information, as shown in FIGS.7B and 7C, in a table. For example, the information shown in FIG. 7B maybe stored when the semiconductor memory device 200 operates in the X8data width option, and the information shown in FIG. 7C may be storedwhen the semiconductor memory device 200 operates in the X4 data widthoption. Referring to FIGS. 7B and 7C, a control code may be generatedeven when the semiconductor memory device 200 operates in another datawidth option, e.g., the X16 data width option. The information describedabove may be stored in a desired (or, alternatively a predetermined)storage unit (e.g., a nonvolatile storage unit such as nonvolatilememory 272) inside or outside the semiconductor memory device 200 andloaded in the control code generator 284 when the semiconductor memorydevice 200 operates, or may be nonvolatilely stored in the control codegenerator 280.

In addition, FIG. 7B shows an example in which data is input and outputvia first to eighth input/output nodes DQ0 to DQ7. First, the selectionsignal SEL as shown in FIG. 7B will be described. As shown, theselection signal SEL includes 5 bits in this embodiment—a master fuse MFbit, a X4 bit, a CA11 bit and F1, F2 and F3 bits. The MF bit indicateswhether a defective memory cell was detected. A 0 indicates no defectivememory cell, and a 1 indicates a defective memory cell. The X4 bit when1 indicates the data width is 4, and when 0 indicates, in this example,the data width is 8. The CA11 bit indicates whether the X4 data widthoperating mode is an even operation mode or an odd operation mode.Because FIG. 7B does not illustrate X4 operation, the CA11 bit is “don'tcare” in this example. However, in the odd operating mode, data isinput/output via the odd input/output nodes DQ, and in the evenoperating mode, data is input/output via the even input/output nodes DQ.The F1, F2, and F3 bits collectively identify one of the first to eighthmemory cell group MCG1 (211_1) to MCG8 (211_8) including the defectivememory cell.

The X4 bit and CA11 bit comprise the mode information received from thenonvolatile memory 272 by the column comparator 288. The columncomparator 288 determines the MF bit and the F0, F1, and F2 bits basedon whether a defective memory cell is detected. If the detection ispositive, the MF bit is set to 1. Then, depending on the memory cellgroup including the defective memory cells, as indicated by the columnaddress, the column comparator generates the F0, F1 and F2 bits toindicate the memory cell group as shown in FIG. 7B. The collection ofthe MF bit, the X4 bit, the CA11 bit, the F2 bit, the F1 bit and the F0bit are output by the column comparator 288 as the selection signal SEL.

The code generator 284 maps the selection signal into a control code orcontrol signal having a bit associated with each selection unit 430_1 to430_8 of the data line selection circuit. In the table of FIG. 7B, thebits under the columns having the headings DQ0 to DQ7 are associatedwith the first to eighth selection units 430_1 to 430_8. A 0 indicatesthat the selection unit 430 did not perform a shift operation, while a 1indicates the selection unit 430 did perform a shift operation.Accordingly, a 0 in the DQ1 column controls the second selection unit430_2 to not perform a shift operation, and to provide a data pathbetween the second memory cell group 211_2 and the second input/outputnode DQ1. By contrast, a 1 in the DQ1 column controls the secondselection unit 211_2 to perform a shift operation and provide a datapath between the first memory cell group 211_1 and the secondinput/output node DQ1.

For example, when an address input for access is of a normal cell, theMF bit may be 0, and in this case, a data line shifting operation is notperformed. Also, since no defective cell exists, the remaining bits ofthe selection signal SEL are “don't care”. Otherwise, when the inputaddress is of a defective cell, a MF bit is set to 1, and in this case,a shifting operation of at least one data line is controlled accordingto a control code shown in FIG. 7B.

If a defective cell is detected in the fifth memory cell group 211_5,the selection units 430_1 to 430_5 corresponding to the first to fifthinput/output nodes DQ0 to DQ4 may perform shifting of data lines toblock data in the defective cell from being transferred through the datalines, and selection units 430_6 to 430_8 corresponding to the sixth toeighth input/output nodes DQ5 to DQ7 may normally output data withoutshifting data lines. Namely, the first selection unit 430_1 provides adata path from the redundancy global data line of the redundancy memorycell group 215 to the first input/output node DQ0, the second thoughfifth selection units 4302 to 430_5 provide data paths from global datalines of the first to fourth memory cell groups 211_1 to 211_4 to thesecond to fifth input/output nodes DQ1 to DQ4, respectively, and thesixth to eighth selection units 430_6 to 430_8 provide data paths fromthe global data lines of the sixth to eighth memory cell groups 211_6 to211_8 to the sixth to eighth input/output nodes DQ5 to DQ7,respectively.

As shown in FIG. 7C, when the semiconductor memory device 200 of FIG. 7Aoperates in the X4 option, a different table in the code generator 284may be used. For example, the information indicating whether the X4option is selected may be set as a logic high value (e.g., 1), and theinformation about the eleventh column address CA11 for an even/oddselection of data may be set. Namely, the mode information in theselection signal SEL indicates to use the X4 table in the code generator284. In addition, since only four input and output units are used, aportion (e.g., F0) of the fuse information F0 to F2 related to the inputand output unit information may be set any one of logic low and logichigh (e.g., “don't care”).

The thermometer code described above is an example of a control code forcontrolling the data line selection circuit 260, and the data lineselection circuit 260 may be controlled by another control codegeneration method or controlled by thermometer codes set as differentvalues.

Still further, it will be appreciated, that instead of the F0, F1 and F2bits, the selection signal may instead include the control signal orcode. Namely, the column comparator 288 may directly generate thecontrol signal as the selection signal. In this embodiment, the codegenerator is not necessary, and the selection signal is applied to thedata line selection circuit 260.

FIG. 7D illustrates a modification to the above described embodiments.For the purposes of simplifying the explanation, the memory cell array210 includes four memory cell groups 211_1 to 211_4 and the data lineselection circuit 260 includes four selection units 430_1 to 430_4. Asshown, instead of shifting all of the redundant global bit lines of theredundant memory cell group to replace global bit lines of a memory cellgroup, less than all or even only one (as shown) redundant data line maybe shifted.

FIG. 7E is a block diagram illustrating an example in which ademultiplexer (DEMUX) is arranged for the redundancy memory cell group215. In FIG. 7E, only the fourth memory cell group 211_4, the redundancymemory cell group 215, and the third and fourth selection units 430_3and 430_4 are illustrated for convenience of explanation.

As illustrated in FIG. 7E, when 8 global data lines are included for thefourth memory cell group 211_4 and a single redundancy global data lineis included for the redundancy memory cell group 215, a 1:8 DEMUX 450may be arranged to demultiplex the data of the single redundancy globaldata line of the redundancy memory cell group 215. In other words, 8MUXes may be disposed for each of the third and fourth selection units430_3 and 430_4, and an output of the 1:8 DEMUX 450 may be provided toeach of the 8 MUXes included in the fourth selection unit 430_4. The 1:8DEMUX 450 may be controlled by the selection control logic 270 based onthe determined location of a detected defective memory cell.

For example, when a memory cell connected to a fourth global data lineof the fourth memory cell group 211_4 is a defective cell, data of thefourth memory cell group 211_4 may be output via first through thirdMUXes and fifth through eighth MUXes of the fourth selection unit 430_4.On the other hand, data of the redundancy memory cell group 215 may beoutput via a fourth MUX of the fourth selection unit 430_4. Moreover, asdescribed above, switching operations of the third and fourth selectionunits 430_3 and 430_4 may be controlled according to control codes.

FIGS. 7F and 7G are block diagrams of a semiconductor memory device 1500according to another embodiment of the inventive concept.

Referring to FIG. 7F, the semiconductor memory device 1500 may include amemory cell array 1510, a column decoder 1520, at least one selectionunit, namely, first through fourth selection units 1531 through 1534,and at least one buffer unit, namely, first through fourth buffer units1541 through 1544. For convenience of explanation, the first throughfourth selection units 1531 through 1534 are arranged outside the columndecoder 1520. Although not shown in FIGS. 7F and 7G, switchingoperations of the first through fourth selection units 1531 through 1534may be controlled based on the aforementioned selection signal SEL orthe control codes generated in response to the selection signal SEL.

The memory cell array 1510 may include a plurality of memory cellgroups, namely, first through fourth memory cell groups 1511 through1514. The memory cell array 1510 may further include a redundancy memorycell group 1515 for replacing defective cells generated in the firstthrough fourth memory cell groups 1511 through 1514. The first throughfourth selection units 1531 through 1534 may operate in the same orsimilar manner as the first through fourth selection units 430_1 through430_8 of FIG. 6B. In other words, the first through fourth selectionunits 1531 through 1534 may perform selection with respect to globaldata lines connected to the first through fourth memory cell groups 1511through 1514 and redundancy global data lines connected to theredundancy memory cell group 1515, and block input and output of thedata of a defective cell and instead allow data of a redundancy cell tobe input and output by selection of the global data lines.

Data may be input to and output to the first selection unit 1531 via thefirst buffer unit 1541. Similarly, data may be input to and output tothe second through fourth selection units 1532 through 1534 via thesecond through fourth buffer units 1542 through 1544, respectively. FIG.7G illustrates the first through fourth buffer units 1541 through 1544in greater detail. As illustrated in FIG. 7G, the first through fourthbuffer units 1541 through 1544 may include sense amplifiers (SAs) 1541_1through 1544_1, respectively, and write drivers (WDs) 1541_2 through1544_2, respectively. The SAs 1541_1 through 1544_1 amplify output datareceived via the first through fourth selection units 1531 through 1534,respectively, and provide amplified data to the outside, and the WDs1541_2 through 1544_2 provide received data to data lines via the firstthrough fourth selection units 1531 through 1534, respectively. Thenumber of SAs 1541_1 through 1544_1 and the number of WDs 1541_2 through1544_2 may be identical to that of global data lines.

A semiconductor memory device 1600 of FIG. 7H is the same as thesemiconductor memory device 1500 of FIGS. 7F and 7G except for locationsof selection units and buffer units. For example, as illustrated in FIG.7H, the semiconductor memory device 1600 may include a memory cell array1610 and a column decoder 1620, and the memory cell array 1610 mayinclude first through fourth memory cell groups 1611 through 1614 and aredundancy memory cell group 1615. At least one buffer unit, namely,first through fourth buffer units 1631 through 1634 and a redundancybuffer unit 1635, may be connected to global data lines and a redundancyglobal data line of the memory cell array 1610, and data output via thefirst through fourth buffer units 1631 through 1634 and the redundancybuffer unit 1635 may be provided to the outside via at least oneselection unit, namely, first through fourth selection units 1641through 1644, or externally input data may be provided to the firstthrough fourth buffer units 1631 through 1634 and the redundancy bufferunit 1635 via the first through fourth selection units 1641 through1644. The first through fourth buffer units 1631 through 1634 correspondto the first through fourth memory cell groups 1611 through 1614, andthe redundancy buffer unit 1635 corresponds to the redundancy memorycell group 1615. The first through fourth selection units 1641 through1644 of FIG. 7H may operate in the same or similar manner as the firstthrough eighth selection units 430_1 through 430_8 of FIG. 6B.

According to the embodiment of FIG. 7H, lines that transmit dataconverted into a CMOS level via the first through fourth buffer units1631 through 1634 and the redundancy buffer unit 1635 are shifted. Inother words, defective cells may be replaced by redundancy cells byshifting of data lines between the first through fourth buffer units1631 through 1634 and the redundancy buffer unit 1635 and I/O pads foran external interface of a semiconductor memory device.

FIG. 8 is a circuit diagram illustrating a repair operation incorrespondence with various data width options, according to anembodiment of the inventive concepts. As shown in FIG. 8, asemiconductor memory device 500 may include a plurality of memory cellgroups, e.g., first to eighth memory cell groups, a redundancy cellgroup 521, and a plurality of selection units, e.g., first to eighthselection units 531 to 538, for repairing defective cells by shiftingdata lines. FIG. 8 shows an example in which a single bit line of eachof the first to eighth memory cell groups is selected by the same columnselection signal to output first to eighth data DQ0 to DQ7. In addition,FIG. 8 shows an example in which a defective cell in the first to eighthmemory cell groups is repaired. In addition, FIG. 8 shows an example inwhich each of the first to eighth selection units 531 to 538 includes a3:1 MUX.

Although FIG. 8 shows an example in which first to eighth data outputfrom the first to eighth memory cell groups are transferred throughfirst to eighth input/output nodes DQ0 to DQ7, when the X16 data widthoption is set, ninth to sixteenth data (not shown) may be output fromeight additional memory cell groups and a redundancy memory cell groupcorresponding thereto. In this case, in response to an address from theoutside, the entire sixteen memory cell groups may be selected tosimultaneously output sixteen pieces of data.

A connection structure between global data lines and first to eighthselection units 531 to 538 in the semiconductor memory device 500 ofFIG. 8 will now be described. For convenience of description, globaldata lines for transferring data in the first to eighth memory cellgroups are named as first to eighth global data lines, respectively, andglobal data lines for transferring data in the redundancy memory cellgroup 521 are named as redundancy global data lines. Although eachglobal data line is shown as a single solid line in FIG. 8, a singleglobal data line in FIG. 8 may substantially include a plurality ofglobal data lines. For example, in the first memory cell group, any oneof eight bit lines is selected in response to a single column selectionsignal, wherein the first global data line may include eight global datalines corresponding to the eight bit lines. According to the selectedbit line, data is output through any one of the eight global data linesincluded in the first global data line.

Each of the first to eighth selection units 531 to 538 may be connectedto at least three global data lines. Exceptionally, the first selectionunit 531 located at the edge is connected to the first global data lineand twice to a redundancy global data line. According to the 3:1 MUXstructure, the redundancy global data line may be connected to twoselection nodes of the first selection unit 531.

Similarly, the second selection unit 532 is connected to the redundancyglobal data line and the first and second global data lines. Inaddition, the third selection unit 533 is connected to the first tothird global data lines, . . . , the eighth selection unit 538 isconnected to the sixth to eighth global data lines.

When the semiconductor memory device 500 operates in the X8 data widthoption, according to the switch arrangement pattern shown in FIG. 8,only two switches from the left of a MUX included in each of the firstto eighth selection units 531 to 538 may operate, wherein the remainingswitch to the right may maintain an off state. Accordingly, when adefective cell is repaired, a shifting operation may be performed inunits of single global data lines.

For example, when data in the first to eighth memory cell groups isaccessed by the same column selection signal, in which a defective cellin the fifth memory cell group 515 is accessed, data in the redundancymemory cell group 521 and the first to fourth memory cell groups 511 to514 is output as first to fifth data to DQ0 to DQ4. In addition, a dataoutput from the fifth memory cell group 515 is blocked, and data in thesixth to eighth memory cell groups 516 to 518 is output as sixth toeighth data to DQ5 to DQ7.

When the semiconductor memory device 500 operates in the X4 data widthoption, only two switches from the right of a MUX included in each ofthe first to eighth selection units 531 to 538 may operate. When adefective cell is accessed, a data line shifting operation for repairingthe defective cell is performed. In the case of FIG. 8, the shiftingoperation may be performed in a group unit of two global data lines.

Examples of the data line shifting operation will now be described indetail with reference to FIGS. 9A to 9C and 10.

FIGS. 9A to 9C are circuit diagrams for describing operations of thesemiconductor memory device 500 of FIG. 8. FIG. 9A shows a case wherethe semiconductor memory device 500 operates in the X8 data widthoption, wherein a defective cell in the fifth memory cell group 515 isaccessed.

According to a switching operation of the first to eighth selectionunits 531 to 538, a shifting operation with respect to the redundancyglobal data line and the first to fourth global data lines is performed.For example, the first selection unit 531 selectively outputs datareceived through the redundancy global data line, and the second tofifth selection units 532 to 535 selectively output data receivedthrough the first to fourth global data lines.

In addition, a data output through the fifth global data line isblocked, and data received through the sixth to eighth global data linesis output as sixth to eighth data to DQ5 to DQ7 without a shiftingoperation. According to the example of FIG. 9A, even though a defectivecell occurs in any one of the first to eighth memory cell groups, theweak cell may be repaired by the single redundancy memory cell group521.

FIG. 9B shows a case where the semiconductor memory device 500 operatesin the X4 data width option, wherein a defective cell in the fifthmemory cell group 515 is accessed.

According to the X4 data width option, data is transmitted and receivedthrough four of the eight selection units. For example, data transferredthrough oddth global data lines may be output as first to fourth data tothe first, third, fifth and seventh input/output nodes DQ0, DQ2, DQ4 andDQ6, also referred to as the first to fourth odd mode input/output nodesDQO0, DQO1, DQO2 and DQO3. In this case, for a memory access, aneleventh column address CA11 may be additionally used, and for example,the first, third, fifth, and seventh memory cell groups 511, 513, 515,and 517 may be accessed.

According to the example described above, a plurality of memory cellgroups (e.g., the first to eighth memory cell groups) may be classifiedinto an even area and an odd area, and a defective cell in the even areaor the odd area may be repaired using a single redundancy cell. That is,on the basis of a shifting operation, a defective cell in any one offour memory cell groups may be repaired using a single redundancy globaldata line.

When a defective cell in the fifth memory cell group 515 of the odd areais accessed, a data line shifting operation is performed by a switchingoperation of the first, third, fifth, and seventh selection units 531,533, 535, and 537. For example, data transferred through the redundancyglobal data line is output as first data to DQ0 by a switching operationof the first selection unit 531.

Since the first global data line is shifted in a group unit of twoglobal data lines, data transferred through the first global data lineis output as second data to DQ2 (DQO1) by a switching operation of thethird selection unit 533. Similarly, data transferred through the thirdglobal data line is output as third data to DQ4 (DQO2) by a switchingoperation of the fifth selection unit 535. However, an output of datathrough the fifth global data line corresponding to the fifth memorycell group 515 is blocked, and data in the seventh memory cell group 517is output as fourth data to DQ6 (DQO3) through the seventh global dataline and the seventh selection unit 537.

According to the X4 data width option shown in FIG. 9B, data in thesecond, fourth, sixth, and eighth memory cell groups 512, 514, 516, and518 of the even area is not accessed. Although FIG. 9B shows an examplein which the second, fourth, sixth, and eighth selection units 532, 534,536, and 538 corresponding to the even area select corresponding globaldata lines, since access to the second, fourth, sixth, and eighth memorycell groups 512, 514, 516, and 518 is blocked, and data transfer throughcorresponding input and output pins DQ is also blocked, the second,fourth, sixth, and eighth selection units 532, 534, 536, and 538 mayselect the second, fourth, sixth, and eighth global data lines,respectively. As another example, the second, fourth, sixth, and eighthselection units 532, 534, 536, and 538 may select no global data linesin a switching operation.

FIG. 9C shows a case where the semiconductor memory device 500 operatesin the X4 data width option, wherein a defective cell in the fourthmemory cell group 514 is accessed.

According to the X4 data width option, the memory cell groups in theeven area (e.g., the second, fourth, sixth, and eighth memory cellgroups 512, 514, 516, and 518) may be accessed (e.g., even operationmode), and accordingly, data transferred through the eventh global datalines may be output at the second, fourth, sixth and eighth input/outputnodes DQ1, DQ3, DQ5 and DQ7, also referred to as the first to fourtheven input/output nodes DQE0 to DQE3. The eleventh column address CA11may be additionally used for memory access according to the X4 datawidth option, and in this case, a defective cell in the second, fourth,sixth, and eighth memory cell groups 512, 514, 516, and 518 may beflexibly repaired using a single redundancy global data line.

When a defective cell in the fourth memory cell group 514 is accessed, adata line shifting operation is performed by a switching operation ofthe second, fourth, sixth, and eighth selection units 532, 534, 536, and538. For example, data transferred through the redundancy global dataline is output as first data to DQE0 by a switching operation of thesecond selection unit 532. In addition, data transferred through thesecond global data line is output as second data to DQE1 by a switchingoperation of the fourth selection unit 534.

However, a data output through the fourth global data line is blocked,and data through the sixth and eighth global data lines is output asthird and fourth data to DQE2 and DQE3 through the sixth and eighthselection units 536 and 538 without a shifting operation.

FIG. 10 shows a case where the semiconductor memory device 500 operatesin the X16 option. As shown in FIG. 10, first to sixteenth data areoutput to input/output nodes DQ0 to DQ15 by accessing sixteen memorycell groups, wherein a defective cell in eight memory cell groupsincluded in a first memory cell array 501 may be repaired using oneredundancy memory cell group 521, and a defective cell in eight memorycell groups included in a second memory cell array 502 may be repairedusing another redundancy memory cell group 522. When the semiconductormemory device 500 operates in the X16 data width option, access to thesixteen memory cell groups is performed, and accordingly, data in thesixteen memory cell groups may be output as first to sixteenth data DQ0to DQ15. However, when the semiconductor memory device 500 operates inthe X8 data width option, only one of the first and second memory cellarrays 501 and 502 may be accessed. For example, the first memory cellarray 501 is accessed, and accordingly, data in memory cell groupsincluded in the first memory cell array 501 may be output.

In the current embodiment, in both the X16 data width option and the X8data width option, a defective cell in eight memory cell groups may beflexibly repaired through a single redundancy global data line. That is,when a defective cell occurs in a particular memory cell group, repairmay be performed by performing a shifting operation in units of singleglobal data line even though a defective cell occurs in any location ofeight memory cell groups. In addition, in the X4 data width option, adefective cell in four memory cell groups may be flexibly repairedthrough a single redundancy global data line according to selectedmemory cell groups. For example, a defective cell in an even area or anodd area may be repaired through a single redundancy global data line.

FIG. 11 is a block diagram of a semiconductor memory device 600according to another embodiment of the inventive concepts. FIG. 11 showsan example in which a repair operation is performed in correspondencewith various data width options, and a data line shifting operation forrepair is performed in both directions unlike the one-directionalshifting in the embodiments described above. In addition, FIG. 11 showsan example in which four memory cell groups 611 to 614 and tworedundancy memory cell groups 621 and 622 are included in a memory cellarray 610, and first to fourth selection units 631 to 634 are arrangedin correspondence with the four memory cell groups 611 to 614.

As shown in FIG. 11, first to fourth input/output nodes DQ0 to DQ3 areconnected to the first to fourth selection units 631 to 634. A switchingoperation of the first selection unit 631 is performed with a firstredundancy global data line and first and second global data linesconnected thereto. Similarly, first to third global data lines areconnected to the second selection unit 632, second to fourth global datalines are connected to the third selection unit 633, and third andfourth global data lines and a second redundancy global data line areconnected to the fourth selection unit 634.

In the embodiment of FIG. 11, since the two redundancy memory cellgroups 621 and 622 are arranged in correspondence with a desired (or,alternatively a predetermined) number of memory cell groups, defectivecells in at least two memory cell groups may be simultaneously repaired.That is, even when a fault simultaneously occurs in two of memory cellsaccessed in response to a single column selection signal, the two memorycells may be simultaneously repaired. In more detail, a defective cellin memory cell groups corresponding to a half of the entire memory cellgroups may be repaired using one redundancy memory cell group, and adefective cell in memory cell groups corresponding to the remaining halfmay be repaired using the other redundancy memory cell group. Operationsof the semiconductor memory device 600 of FIG. 11 will now be describedin detail with reference to FIGS. 12 to 14.

FIG. 12 is a circuit diagram of an example of the semiconductor memorydevice 600 of FIG. 11. FIG. 12 shows an example in which the first andsecond redundancy memory cell groups 621 and 622 are arranged incorrespondence with first to eighth memory cell groups. In addition,first to eighth selection units 631 to 638 are arranged incorrespondence with the first to eighth memory cell groups, and when theX8 option is selected, first to eighth data to first eighth input/outputnodes DQ0 to DQ7 are output through the first to eighth selection units631 to 638. As in the embodiment described above, when the semiconductormemory device 600 operates in the X16 option, ninth to sixteenth data(not shown) are output by accessing other eight memory cell groups (notshown).

The first redundancy memory cell group 621 is used to repair a defectivecell in four memory cell groups. For example, the first redundancymemory cell group 621 is used to repair a defective cell in the first tofourth memory cell groups, and the second redundancy memory cell group622 is used to repair a defective cell in the fifth to eighth memorycell groups. As shown in FIG. 12, a defective cell in the second memorycell group 612 is repaired using the first redundancy memory cell group621, and a defective cell in the fifth memory cell group 615 is repairedusing the second redundancy memory cell group 622.

FIGS. 13A to 13C are circuit diagrams for describing operations of thesemiconductor memory device 600 of FIG. 12 in the X8 and X4 data widthoptions. FIG. 13A shows an example in which the X8 data width option isset. When a defective cell in the second memory cell group 612 isaccessed, an output of data in the second memory cell group 612 isblocked, and instead, data transferred through a first redundancy globaldata line corresponding to the first redundancy memory cell group 621 isoutput as first data DQ0 through the first selection unit 631.Similarly, data transferred through a first global data line is outputas second data DQ1 through the second selection unit 632 by a shiftingoperation of the first global data line. Data transferred through thirdand fourth global data lines is output as third and fourth data to DQ2and DQ3 without a shifting operation.

A defective cell in the fifth memory cell group 615 is repaired usingthe second redundancy memory cell group 622. Data transferred throughthe second redundancy global data line corresponding to the secondredundancy memory cell group 622 is output as eighth data to DQ7 throughthe eighth selection unit 638. Similarly, a shifting operation of sixthto eighth global data lines is performed, and accordingly, datatransferred through the sixth to eighth global data lines is output asfifth to seventh data to DQ4 to DQ6 through the fifth to seventhselection units 635 to 637.

FIGS. 13B and 13C show examples in which the semiconductor memory device600 operates in the X4 data width option. As shown in FIG. 13B, when adefective cell in any one of four memory cell groups on the left isaccessed, the defective cell is repaired using the first redundancymemory cell group 621. However, as shown in FIG. 13C, when a defectivecell in any one of four memory cell groups on the right is accessed, thedefective cell is repaired using the second redundancy memory cell group622.

Referring to FIG. 13B, when the X4 option is set, four memory cellgroups may be simultaneously accessed. For example, eight memory cellgroups are classified into an even area and an odd area. Data in thesecond, fourth, sixth, and eighth memory cell groups included in theeven area may be accessed, and the accessed data is output as first tofourth data DQO0 to DQO3. As shown in FIG. 13B, a defective cell in thefourth memory cell group 614 of the even area is repaired using thefirst redundancy memory cell group 621, and an output of data in thefourth memory cell group 614 is blocked by a data line shiftingoperation. Data transferred through the first redundancy global dataline corresponding to the first redundancy memory cell group 621 isoutput as first data to DQO0 through the first selection unit 631. Inaddition, data transferred through the second global data line connectedto the second memory cell group 612 is output as second data to DQO1through the third selection unit 633.

The global data lines arranged in the right of FIG. 13B are shifted inthe opposite direction (e.g., the left direction in FIG. 13B), andaccordingly, data transferred through the sixth and eighth global datalines respectively connected to the sixth and eighth memory cell groupsis output as third and fourth data to DQO2 and DQO3 through the fifthand seventh selection units 635 and 637.

FIG. 13C shows an example in which the first, third, fifth, and seventhmemory cell groups in the odd area are accessed, and a defective cell inthe fifth memory cell group 615 is repaired. As shown in FIG. 13C, torepair the defective cell in the fifth memory cell group 615, datatransferred through the second redundancy global data line correspondingto the second redundancy memory cell group 622 is output as fourth datato DQE3 through the eighth selection unit 638. In addition, data in thefirst, third, and seventh memory cell groups in which no defective celloccurs is output as first to third data to DQE0 to DQE2 through thesecond, fourth, and sixth selection units 632, 634, and 636,respectively.

FIG. 14 shows an example in which the semiconductor memory device 600operates in the X16 data width option, wherein data from a first cellarray 610_1 and a second cell array 610_2 is accessed and output asfirst to sixteenth data to DQ0 to DQ15. The first cell array 610_1includes a plurality of memory cell groups and the first and secondredundancy memory cell groups 621 and 622. Similarly, the second cellarray 610_2 includes a plurality of memory cell groups and third andfourth redundancy memory cell groups 623 and 624.

A data line selection block 630 includes a plurality of selection units(not shown) that may perform the switching operations as described inFIGS. 13A, 13B, and 13C. Accordingly, a defective cell is blocked frombeing accessed and output to the outside on the basis of a data lineselection operation, and instead, data obtained by accessing the firstto fourth redundancy memory cell groups 621 to 624 is output. When thesemiconductor memory device 600 operates in the X8 data width option,any one of the first and second cell arrays 610_1 and 610_2 may beaccessed, and when the semiconductor memory device 600 operates in theX4 data width option, a half of the plurality of memory cell groups inany one of the first and second cell arrays 610_1 and 610_2 may beaccessed.

According to the embodiment described above, redundancy memory cellgroups are arranged on both sides (e.g., the left and right) of one cellarray, and repair may be performed using any one of the redundancymemory cell groups according to a location of a defective cell. Inaddition, two defective cells may be simultaneously accessed, and inthis case, the two defective cells may be simultaneously repaired usingthe two redundancy memory cell groups. For example, a defective cell inmemory cell groups of an even area may be repaired using any one of thetwo redundancy memory cell groups according to a location of a memorycell group including the defective cell.

FIG. 15 is a block diagram of a semiconductor memory device 700according to another embodiment of the inventive concepts. FIG. 15 showsan example in which a defective cell is repaired in various data widthoptions even when a data line selection block uses 2:1 MUXs.

As shown in FIG. 15, the semiconductor memory device 700 may include aplurality of memory cell groups (e.g., first to fourth memory cellgroups 711 to 714), wherein the first to fourth memory cell groups 711to 714 may be classified into a plurality of areas (e.g., an even areaand an odd area). In addition, the semiconductor memory device 700 mayinclude a redundancy memory cell group 721 for repairing a defectivecell in the first to fourth memory cell groups 711 to 714. In addition,the semiconductor memory device 700 may include first to fourthselection units 731 to 734 as the data line selection block and aneven/odd selection unit 740 for selecting repair of the even area or theodd area. A redundancy global data line may be connected to the first orsecond selection unit 731 or 732 on the basis of a switching operationof the even/odd selection unit 740.

In the embodiment of FIG. 15, since repair is performed on the basis ofeven or odd areas, a data line shifting operation may be performed in agroup unit of two global data lines. Accordingly, the third selectionunit 733 is connected to first and third global data lines connected tothe first and third memory cell groups 711 and 713, and the fourthselection unit 734 is connected to second and fourth global data linesconnected to the second and fourth memory cell groups 712 and 714. Thefirst selection unit 731 is connected to the redundancy global data lineconnected to the redundancy memory cell group 721 and the first globaldata line connected to the first memory cell group 711, and the secondselection unit 732 is connected to the redundancy global data lineconnected to the redundancy memory cell group 721 and the second globaldata line connected to the second memory cell group 712.

According to the embodiment of FIG. 15, when a defective cell in the oddarea (e.g., the first and third memory cell groups 711 and 713) isrepaired, the redundancy global data line is connected to the firstselection unit 731 on the basis of a switching operation of the even/oddselection unit 740, and when a defective cell in the even area (e.g.,the second and fourth memory cell groups 712 and 714) is repaired, theredundancy global data line is connected to the second selection unit732 on the basis of a switching operation of the even/odd selection unit740. Accordingly, a defective cell may be repaired in various data widthoptions, such as the X4, X8, and X16 data width options, using 2:1 MUXs,and operations related thereto will now be described in detail withreference to FIGS. 16, 17A, and 17B.

As shown in FIG. 16, the semiconductor memory device 700 may include aplurality of memory cell groups, the redundancy memory cell group 721,and first to eighth selection units 731 to 738 for shifting data linesto repair a defective cell. The semiconductor memory device 700 mayfurther include the even/odd selection unit 740 for selecting the evenarea or the odd area, wherein each of the first to eighth selectionunits 731 to 738 and the even/odd selection unit 740 may include atleast one 2:1 MUX. Alternatively, the even/odd selection unit 740 mayinclude a pair of transistors. The even/odd selection unit 740 may becontrolled based on the even/odd operation mode indicated, for example,by the CA11 bit stored in the selection control logic 270. Stillfurther, the even/odd selection unit 740 may be eliminated in favor ofdirect connections of the redundant global data line to the first andsecond selection units 731 and 732; however, use of the even/oddselection unit 740 reduces load on the selection units 731 and 732.

FIG. 16 shows an example in which first to eighth data DQ0 to DQ7 areoutput from eight memory cell groups according to the X8 or X16 datawidth options. If a defective cell in a fifth memory cell group 715 ofthe odd area is accessed, data transferred through a redundancy globaldata line is input to the first selection unit 731 on the basis of aswitching operation of the even/odd selection unit 740 and is output asfirst data to DQ0.

A shifting operation between global data lines corresponding to memorycell groups in the odd area is performed on the basis of a switchingoperation of the selection units 731 to 738, and accordingly, thedefective cell in the fifth memory cell group 715 is repaired. Forexample, data transferred through a first global data line is output asthird data to DQ2 through the third selection unit 733, and datatransferred through a third global data line is output as fifth data toDQ4 through the fifth selection unit 735. An output of data transferredthrough a fifth global data line connected to the defective cell isblocked, and data transferred through a seventh global data line isoutput as seventh data to DQ6 through the seventh selection unit 737.

A shifting operation of global data lines corresponding to memory cellgroups in the even area does not have to be performed, and accordingly,data transferred through second, fourth, sixth, and eighth global datalines corresponding to second, fourth, sixth, and eighth memory cellgroups may be output through the second, fourth, sixth, and eighthselection units 732, 734, 736, and 738.

FIGS. 17A and 17B show examples in which the semiconductor memory device700 operates in the X4 data width option. FIG. 17A shows an example inwhich a defective cell occurs in a memory cell group of the odd area,and FIG. 17B shows an example in which a defective cell occurs in amemory cell group of the even area.

As shown in FIG. 17A, when a defective cell occurs in the fifth memorycell group 715 belonging to the odd area, data transferred through theredundancy global data line is output as first data to DQO0 through thefirst selection unit 731 on the basis of a switching operation of theeven/odd selection unit 740. In addition, a shifting operation isperformed up to the fifth memory cell group 715 including the defectivecell, and accordingly, data transferred through the first and thirdglobal data lines are output as second and third data to DQO1 and DQO2through the third and fifth selection units 733 and 735, respectively.Data transferred through the seventh global data line is output asfourth data to DQO3 through the seventh selection unit 737.

Access to the memory cell groups belonging to the even area is notperformed, and accordingly, the selection units corresponding to theeven area (e.g., the second, fourth, sixth, and eighth selection units732, 734, 736, and 738) may maintain a switching connection state of thecorresponding global data lines (e.g., the second, fourth, sixth, andeighth global data lines) or may block connections thereof.

As shown in FIG. 17B, when a defective cell occurs in a fourth memorycell group 714 belonging to the even area, data transferred through theredundancy global data line is output as first data to DQE0 through thesecond selection unit 732 on the basis of a switching operation of theeven/odd selection unit 740. In addition, a shifting operation isperformed up to the fourth memory cell group 714 including the defectivecell, and accordingly, data transferred through the second global dataline is output as second data to DQE1 through the fourth selection unit734. Data transferred through the sixth and eighth global data lines areoutput as third and fourth data to DQE2 and DQE3 through the sixth andeighth selection units 736 and 738, respectively.

FIG. 18 is a block diagram of a semiconductor memory device 800according to another embodiment of the inventive concepts. FIG. 18 showsan example in which a weak cell is repaired in various data width modeseven when a data line selection block uses 2:1 MUXs, wherein weak cellsin two memory cell groups are simultaneously repaired.

As shown in FIG. 18, the semiconductor memory device 800 may include aplurality of memory cell groups (e.g., first to fourth memory cellgroups 811 to 814) and a plurality of redundancy memory cell groups(e.g., first and second redundancy memory cell groups 821 and 822). Inaddition, the first to fourth memory cell groups 811 to 814 may beclassified into a plurality of areas, e.g., an even area and an oddarea. In addition, the first and second redundancy memory cell groups821 and 822 include the first redundancy memory cell group 821 forrepairing a defective cell in the odd area (e.g., the first and thirdmemory cell groups 811 and 813) and the second redundancy memory cellgroup 822 for repairing a defective cell in the even area (e.g., thesecond and fourth memory cell groups 812 and 814). In addition, thesemiconductor memory device 800 may include first to fourth selectionunits 831 to 834 as a data line selection block.

Although repair of the even or odd area is performed using a singleredundancy memory cell group on the basis of a switching operation ofthe even/odd selection unit 740 in the previous embodiment, according tothe current embodiment, repair of any one memory cell group belonging toone of the even and odd areas is performed using the first redundancymemory cell group 821, and repair of any one memory cell group belongingto the other one area is performed using the second redundancy memorycell group 822. Accordingly, as shown in FIG. 18, a data line shiftingoperation for repair may be performed in a group unit of two global datalines.

A first redundancy global data line corresponding to the firstredundancy memory cell group 821 is connected to the first selectionunit 831, and a first global data line corresponding to the first memorycell group 811 is commonly connected to the first and third selectionunits 831 and 833. In addition, a second redundancy global data linecorresponding to the second redundancy memory cell group 822 isconnected to the fourth selection unit 834, and a fourth global dataline corresponding to the fourth memory cell group 814 is commonlyconnected to the second and fourth selection units 832 and 834.Operations of the semiconductor memory device 800 of FIG. 18 will now bedescribed in detail with reference to FIGS. 19A to 19C.

As shown in FIG. 19A, the semiconductor memory device 800 may include aplurality of memory cell groups, the first and second redundancy memorycell groups 821 and 822, and first to eighth selection units 831 to 838for repairing weak cells by shifting data lines. Each of the first toeighth selection units 831 to 838 may include at least one 2:1 MUX.

FIG. 19A shows an example in which first to eighth data on input/outputnodes DQ0 to DQ7 are output from eight memory cell groups according tothe X8 or X16 options, wherein when defective cells in fifth and sixthmemory cell groups 815 and 816 are accessed, the defective cells arerepaired.

A defective cell in the fifth memory cell group 815 belonging to the oddarea is repaired using the first redundancy memory cell group 821. To doso, a data line shifting operation is performed, and as shown in FIG.19A, data transferred through the first redundancy global data line isoutput as first data to DQ0 through the first selection unit 831. Inaddition, data transferred through a first global data line is output asthird data to DQ2 through the third selection unit 833 by a shiftingoperation, and data transferred through a third global data line isoutput as fifth data to DQ4 through the fifth selection unit 835 by ashifting operation. An output of data transferred through a fifth globaldata line is blocked, and data transferred through a seventh global dataline is output as seventh data to DQ6 through the seventh selection unit837.

A defective cell in the sixth memory cell group 816 belonging to theeven area is repaired using the second redundancy memory cell group 822.To do so, a data line shifting operation is performed, and as shown inFIG. 19A, data transferred through the second redundancy global dataline is output as eighth data to DQ7 through the eighth selection unit838. In addition, data transferred through an eighth global data line isoutput as sixth data to DQ5 through the sixth selection unit 836, and anoutput of data transferred through a sixth global data line is blocked.In addition, data transferred through second and fourth global datalines are output as second and fourth data to DQ1 and DQ3 through thesecond and fourth selection unit 832 and 834, respectively.

FIGS. 19B and 19C show examples in which the semiconductor memory device800 of 19A operates in the X4 data width option. FIG. 19B shows anexample in which a defective cell occurs in a memory cell groupbelonging to the odd area, and FIG. 19C shows an example in which adefective cell occurs in a memory cell group belonging to the even area.

As shown in FIG. 19B, when a defective cell occurs in the fifth memorycell group 815 belonging to the odd area, data transferred through thefirst redundancy global data line is output as first data to DQO0through the first selection unit 831. In addition, a shifting operationis performed up to the fifth memory cell group 815 including thedefective cell, and accordingly, data transferred through the first andthird global data lines are output as second and third data to DQO1 andDQO2 through the third and fifth selection units 833 and 835,respectively. An output of data transferred through the fifth globaldata line is blocked, and data transferred through the seventh globaldata line is output as fourth data to DQO3 through the seventh selectionunit 837.

As shown in FIG. 19C, when a defective cell occurs in the sixth memorycell group 816 belonging to the even area, data transferred through thesecond redundancy global data line is output as fourth data to DQE3through the eighth selection unit 838. In addition, a shifting operationis performed up to the sixth memory cell group 816 including thedefective cell, and accordingly, data transferred through the eighthglobal data line is output as third data to DQE2 through the sixthselection unit 836. An output of data transferred through the sixthglobal data line is blocked, and data transferred through the second andfourth global data lines are output as first and second data to DQE0 andDQE1 through the second and fourth selection units 832 and 834,respectively.

According to the embodiments described above, even though asemiconductor memory device operates using various options, such as theX16, X8, and X4 data width options, defective cells may be repaired, anda defective cell in a plurality of memory cell groups may be repairedusing a single redundancy memory cell group. In addition, by arrangingat least two redundancy memory cell groups per cell array including aplurality of memory cell groups, even when two or more defective cellsare simultaneously accessed, the defective cells may be simultaneouslyrepaired. For example, the plurality of memory cell groups may beclassified into a plurality of areas, such as even and odd areas, andrepair may be performed using a separate redundancy memory cell group ineach area.

FIG. 20 is a block diagram of a semiconductor memory device 900according to another embodiment of the inventive concepts. As shown inFIG. 20, the semiconductor memory device 900 may include one or morecell arrays 910_1 and 910_2 and a data line selection block 930. Thememory cell arrays 910_1 and 910_2 may be on separate chips. A rowdecoder, a column decoder, and other peripheral circuits for a memoryoperation are not shown for convenience of description.

Each of the one or more cell arrays 910_1 and 910_2 may include aplurality of memory cell groups MCGs and a redundancy memory cell groupRMCG. For example, a first cell array 910_1 may include a plurality ofmemory cell groups 911 and a first redundancy memory cell group 921corresponding to the plurality of memory cell groups 911, and a secondcell array 910_2 may include a plurality of memory cell groups 912 and asecond redundancy memory cell group 922 corresponding to the pluralityof memory cell groups 912. When eight memory cell groups are arranged ineach of the first and second cell arrays 910_1 and 910_2, the eightmemory cell groups in the first cell array 910_1 are connected to firstto eighth global data lines GDL11 to GDL18, respectively.

Repair is performed on the basis of a data line selection operation ofthe data line selection block 930. The data line selection block 930 isconnected to a plurality of global data lines GDL11 to GDL18 and GDL21to GDL28 connected to the first and second cell arrays 910_1 and 910_2,respectively, and blocks data in a defective cell from being output andcontrols data in a redundancy cell to be output instead by a data lineselection operation. When a data width option is set to X8, the dataline selection block 930 outputs first to eighth data DQ0 to DQ7 ofwhich repair has been performed.

According to the current embodiment, the data line selection block 930performs a selection operation of global data lines corresponding tomemory cell groups without separately having redundancy global datalines corresponding to the first and second redundancy memory cellgroups 921 and 922. In addition, the first redundancy memory cell group921 may be used to repair a defective cell in the second cell array910_2, and the second redundancy memory cell group 922 may be used torepair a defective cell in the first cell array 910_1. For example, whena defective cell occurs in the first cell array 910_1, data obtained byaccessing the second redundancy memory cell group 922 is transferred toany one global data line in the second cell array 910_2 (e.g., the ninthglobal data line GDL21) according to a column selection operation, andthe data line selection block 930 blocks data in the defective cell frombeing output by performing a data line selection operation and outputsthe data in the second redundancy memory cell group 922 instead. When adefective cell occurs in a third memory cell group of the first cellarray 910_1, the data line selection block 930 blocks data transferredthrough the third global data line GDL13 from being output and outputsdata transferred through the ninth global data line GDL21 instead.

According to the embodiment of FIG. 20, an overhead area for arrangingseparate redundancy global data lines corresponding to the first andsecond redundancy memory cell groups 921 and 922 is not produced. Eachof the first and second redundancy memory cell groups 921 and 922 isconnected to any one of the global data lines by a column selectionoperation. Thus, a defective cell may be repaired by a selectionoperation of global data lines corresponding to any one of the first andsecond cell arrays 910_1 and 910_2 and a global data line connected to aredundancy memory cell group in the other one of the first and secondcell arrays 910_1 and 910_2. Although not shown in FIG. 20, when thesecond cell array 910_2 is accessed, the data line selection block 930outputs first to eighth data to DQ0 to DQ7 by performing a selectionoperation of the ninth to sixteenth global data lines GDL21 to GDL28 andthe eighth global data line GDL18.

FIGS. 21A to 21D are circuit diagrams and block diagrams for describingthe semiconductor memory device 900 of FIG. 20.

As shown in FIG. 21A, the first cell array 910_1 may include a pluralityof memory cell groups and the first redundancy memory cell group 921,and the second cell array 910_2 may include a plurality of memory cellgroups and the second redundancy memory cell group 922. In addition, arow decoder 940 for operating word lines in the first and second cellarrays 910_1 and 910_2 and column decoders 951 and 952 for columnselection operations may be further arranged. In addition, the data lineselection block 930 may include a plurality of selection units. Each ofthe selection units includes at least one MUX, and FIG. 21A shows anexample in which 2:1 MUXs are used. As shown, selection unit 938 isconnected to the eighth global data line GDL18 in the first array 910_1and the first global data line GDL21 in the second array 910_2.Similarly, the selection unit 939 is connected to the eighth global dataline GDL18 in the first array 910_1 and the first global data line GDL21in the second array 910_2.

As described above, a defective cell in the first cell array 910_1 maybe repaired using the second redundancy memory cell group 922 in thesecond cell array 910_2, and data in the second redundancy memory cellgroup 922 may be transferred through a global data line corresponding tothe second cell array 910_2 on the basis of a column selectionoperation. For example, the data in the second redundancy memory cellgroup 922 is transferred through the ninth global data line GDL21 thatis connected to the eighth selection unit 938 corresponding to the firstcell array 910_1. The reverse of this operation, where the firstredundancy memory cell group 921 repairs a defect in the second cellarray 910_2 via the selection unit 939 may also be performed.

FIG. 21B shows an example in which the semiconductor memory device 900of FIG. 21A performs row and column selection operations. As shown inFIG. 21B, the row decoder 940 operates the word lines in the first andsecond cell arrays 910_1 and 910_2, and the column decoder 950 mayinclude first and second column decoders 951 and 952 that respectivelycorrespond to the first and second cell arrays 910_1 and 910_2, andfirst and second redundancy column decoders 953 and 954 thatrespectively correspond to the first and second redundancy memory cellgroups 921 and 922. A row address RA or a decoded row address isprovided to the row decoder 940, and a column address CA of a decodedcolumn address is provided to the column decoder 950.

The row decoder 940 simultaneously enables the word lines in the firstand second cell arrays 910_1 and 910_2 in response to the row addressRA. Accordingly, memory cells (e.g., normal memory cells) in any one ofthe first and second cell arrays 910_1 and 910_2 and redundancy cells inthe other one of the first and second cell arrays 910_1 and 910_2 may besimultaneously selected.

Data in the normal memory cells and data in the redundancy cells may betransferred through data lines by a column selection operation accordingto the column address CA. For example, the column address CA may beprovided to the first column decoder 951 corresponding to the first cellarray 910_1 and the second redundancy column decoder 954 correspondingto the second redundancy memory cell group 922. As described above,according to enabling of a redundancy column selection line, data inredundancy cells may be transferred through a global data line. Forexample, data in the second redundancy memory cell group 922 may betransferred through the ninth global data line GDL21. In addition,whether the redundancy column selection line is enabled may becontrolled by the column address matching operation in the embodimentdescribed above.

FIG. 21C shows an example of a data line shifting operation of the dataline selection block 930 included in the semiconductor memory device 900of FIG. 21A. As in the embodiment described above, on the basis of adata line selection operation of the data line selection block 930,instead of blocking data in a defective cell from being output, data ina redundancy cell is controlled to be output. FIG. 21C shows a casewhere a memory cell connected to the fifth global data line GDL15 is adefective cell, and in this case, data transferred through the first tofourth global data lines GDL11 to GDL14 are output as first to fourthdata to DQ0 to DQ3 through the first to fourth selection units 931 to934, and an output of data transferred through the fifth global dataline GDL15 is blocked. In addition, data transferred through the sixthto eighth global data lines GDL16 to GDL18 are output as fifth toseventh data to DQ4 to DQ6 through the fifth to seventh selection units935 to 937, and data in the second redundancy memory cell group 922 isoutput as eighth data to DQ7 through the ninth global data line GDL21and the eighth selection unit 938.

FIG. 21D shows an example in which a global data line GDL21 is connectedto a redundancy cell. Only one memory cell group 912 is shown in FIG.21D, and the memory cell group 912 includes a plurality of bit lines BLsconnected to memory cells therein. The plurality of bit lines BLs areconnected to the global data line GDL21 on the basis of a columnselection operation of a column selection area 912_1.

Similarly, a redundancy memory cell group 922 includes a plurality ofredundancy bit lines RBLs connected to redundancy cells therein. Aredundancy column selection area 922_1 for connecting the redundancymemory cell group 922 to the global data line GDL21 is further included,and data in the redundancy cells is transferred through the global dataline GDL21 on the basis of a column selection operation of theredundancy column selection area 922_1.

FIG. 22 shows a semiconductor memory device 1100 including one of theembodiments of the inventive concepts. Referring to FIG. 22, thesemiconductor memory device 1100 may include various kinds of circuitblocks for driving a memory cell array and a DRAM cell, and may bemodified to include the repair structure and operation of one of theabove described embodiments.

A timing register 1102 may be enabled when a chip select signal CSchanges from a disable level (e.g., logic high) to an enable level(e.g., logic low). The timing register 1102 may receive command signals,such as a clock signal CLK. A clock enable signal CKE, a chip select barsignal CS, a row address strobe bar signal RAS, a column address strobebar signal CAS, a write enable bar signal WE, and a data input/outputmask signal DQM, and generate various kinds of internal command signalsLRAS, LCBR, LWE, LCAS, LWCBR, LDQM for controlling the circuit blocks byprocessing the received command signals.

Some of the internal command signals generated by the timing register1102 are stored in a programming register 1104. For example, latencyinformation, burst length information, and so forth that are related toa data output may be stored in the programming register 1104. Theinternal command signals stored in the programming register 1104 may beprovided to a latency & burst length controller 1106, and the latency &burst length controller 1106 may provide a control signal forcontrolling latency or a burst length in a data output to a columndecoder 1110 via a column buffer 1108 or to an output buffer 1112.

An address register 1120 may receive an address ADD from the outside. Arow address may be provided to a row decoder 1124 via a row addressbuffer 1122. In addition, a column address may be provided to the columndecoder 1110 via the column buffer 1108. The row address buffer 1122 mayfurther receive a refresh address generated by a refresh counter (notshown) therein in response to refresh commands LRAS and LCBR and mayprovide any one of the row address and the refresh address to the rowdecoder 1124. In addition, the address register 1120 may provide a banksignal for selecting a bank to a bank selection unit 1126.

The row decoder 1124 may decode the row address or the refresh addressreceived from the row address buffer 1122 and enable word lines in amemory cell array 1101. The column decoder 1110 may decode the columnaddress and perform a selection operation of bit lines in the memorycell array 1101. For example, a column selection line may be applied tothe semiconductor memory device 1100 to perform a selection operationfor the column selection line.

A sense amplifier 1130 may amplify data in a memory cell selected by therow decoder 1124 and the column decoder 1110 and provide the amplifieddata to the output buffer 1112. Data to be written in a memory cell maybe provided to the memory cell array 1101 via a data input register1132, and an input/output controller 1134 may control a data transferoperation through the data input register 1132.

FIG. 23 is a block diagram of a memory system 1200 according to anembodiment of the inventive concepts. As shown in FIG. 23, the memorysystem 1200 may include a memory module 1210 and a memory controller1220. The memory module 1210 may include at least one semiconductordevice mounted on a module board, e.g., at least one semiconductormemory device 1212 and a memory management chip 1211 for managing amemory operation. FIG. 23 shows DRAM chips as the at least onesemiconductor memory device 1212, wherein the DRAM chips are structuredto perform a repair operation disclosed in any of the embodimentsdescribed above. For example, each of the DRAM chips may includeredundancy cells to block data in a weak cell from being output andoutput data in a redundancy cell instead on the basis of a data lineshifting operation. The memory controller 1220 provides various signals,e.g., a command/address CMD/ADD and a clock signal CLK, for controllingthe at least one semiconductor device included in the memory module 1210and provides or receives data DQ to or from the memory module 1210 bycommunicating with the memory module 1210.

In the embodiment described above, some of the configurations andoperations performed for a repair operation may be performed by thememory management chip 1211. For example, address information related toa weak cell may be stored in the memory management chip 1211, andaccordingly, row and column addresses for enabling a redundancy cell maybe provided from the memory management chip 1211 to the at least onesemiconductor memory device 1212. In addition, the memory managementchip 1211 may output control codes, such as thermometer codes, forcontrolling a data line shifting operation and provide the control codesto the at least one semiconductor memory device 1212.

FIG. 24 is a block diagram of a semiconductor storage system 1300according to an embodiment of the inventive concepts. The semiconductorstorage system 1300 may include a semiconductor memory device accordingto an embodiment of the inventive concepts.

Referring to FIG. 24, the semiconductor storage system 1300 may includea non-volatile memory device 1310 and various function blocks 1320related thereto. The non-volatile memory device 1310 may include asemiconductor memory device such as a flash memory device and may employthe structure and operation of any of the above described repairembodiments. As the various function blocks 1320, a processor (PROS), aRAM, a cache buffer (CBUF), a memory controller (Ctrl), and a hostinterface (HOST I/F) that are connected via a bus may be included. TheRAM may include a semiconductor memory device according to an embodimentof the inventive concepts. The processor PROS controls the memorycontroller Ctrl to transmit and receive data to and from thenon-volatile memory device 1310 in response to a request (command,address, or data) of a host. The processor PROS and the memorycontroller (Ctrl) in the semiconductor storage system 1300 may beimplemented as a single ARM processor. Data required to operate theprocessor PROS may be loaded in the RAM.

The host interface HOST I/F receives a request of the host and transmitsthe request of the host to the processor PROS, or transmits datareceived from the non-volatile memory device 1310 to the host. The hostinterface HOST I/F may interface with the host using various protocols,such as Universal Serial Bus (USB), Man Machine Communication (MMC),Peripheral Component Interconnect-Express (PCI-E), Serial AdvancedTechnology Attachment (SATA), Parallel Advanced Technology Attachment(PATA), Small Computer System Interface (SCSI), Enhanced Small DeviceInterface (ESDI), and Intelligent Drive Electronics (IDE). Data to betransmitted to the non-volatile memory device 1310 or data received fromthe non-volatile memory device 1310 may be temporarily stored in thecache buffer CBUF.

The non-volatile memory device 1310 may be packaged using various typesof packages, e.g., Package on Package (PoP), Ball grid arrays (BGAs),Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), PlasticDual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, ChipOn Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic MetricQuad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC),Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), ThinQuad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP),Wafer-level Fabricated Package (WFP), and Wafer-Level Processed StackPackage (WSP).

FIG. 25 is a block diagram of a network system 1400 according to anembodiment of the inventive concepts. The network system 1400 mayinclude a semiconductor memory device according to of any of the abovedescribed repair embodiments.

Referring to FIG. 25, the network system 1400 may include a serversystem SSYS and a plurality of terminals TEM1 to TEMn that are connectedto each other over a network. The server system SSYS may include aserver for processing requests received from the plurality of terminalsTEM1 to TEMn connected to the network and a semiconductor memory deviceMEM (e.g., Solid State Drive) for storing data corresponding to thereceived requests. Also, the server may include a semiconductor memorydevice (not shown) according to an embodiment of the inventive concepts.

FIG. 26 is a block diagram of another memory system 1800 to which asemiconductor memory device according to an embodiment of the inventiveconcepts is applied.

Referring to FIG. 26, the memory system 1800 may include a memory module1810 and a memory controller 1820. The memory module 1810 may include atleast one semiconductor memory device 1830 mounted on a module board.The at least one semiconductor memory device 1830 may be implemented bya DRAM chip, and each of the at least one semiconductor memory device1830 may include a plurality of semiconductor layers. The plurality ofsemiconductor layers may include at least one master chip 1831 and atleast one slave chip 1832. A signal may be transmitted between theplurality of semiconductor layers through a through-silicon via (TSV).

Although a structure in which a signal transfer between semiconductorlayers is performed through the TSV is described in the currentembodiment, the current embodiment is not limited thereto, and may alsobe applied to a structure layered through wire bonding, interpose, orwire-formed tapes.

In addition, a signal transfer between semiconductor layers may beperformed by an optical input/output connection. For example, thesemiconductor layers may be connected to each other using a radiativemethod using a radio frequency (RF) wave or an ultrasound wave, aninductive coupling method using magnetic induction, or a non-radiativemethod using magnetic field resonance.

The radiative method is a method of transferring a signal in a wirelessmanner by using an antenna, such as a monopole antenna or a planarinverted-F antenna (PIFA). Radiation occurs while an electric field anda magnetic field varying over time affect each other, and when anantenna of the same frequency exists, a signal may be received to meet apolarization characteristic of an incident wave. The inductive couplingmethod is a method of generating a magnetic field that is strong in onedirection by winding a coil several times and generating coupling byapproaching a coil resonating at a similar frequency to the wound coil.The non-radiative method is a method using evanescent wave coupling bywhich an electronic wave moves between two media resonating with thesame frequency through a near distance magnetic field. Each of themaster chip 1831 and the slave chip 1832 may include a reference voltagegenerator (not shown) according to the embodiments of the inventiveconcepts. The memory module 1810 may communicate with the memorycontroller 1820 via a system bus. Data DQ, command/address CMD/ADD, aclock signal CLK, and so forth may be transmitted and received betweenthe memory module 1810 and the memory controller 1820 via the systembus.

While the inventive concepts has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodthat various changes in form and details may be made therein withoutdeparting from the spirit and scope of the following claims.

We claim:
 1. A memory device, comprising: a memory cell array having atleast a first memory cell group and a redundancy memory cell group, thefirst memory cell group including a plurality of first memory cellsassociated with a first data line, and the redundancy memory cell groupincluding a plurality of redundancy memory cells associated with aredundancy data line; a data line selection circuit; selection controllogic configured to detect if a defective memory cell in the firstmemory cell group is being accessed, and configured to control the dataline selection circuit to replace access via the first data line withaccess via the redundancy data line such that a detected defectivememory cell in the first memory cell group is replaced with one of theplurality of redundancy memory cells, the selection control logicincluding, a storage device configured to store address information fordefective memory cells, the address information including row addressinformation and column address information identifying rows and columnsin the first. Memory cell group including defective memory cells, andcontrol signal generation logic configured to generate a control signalfor controlling the data line selection circuit based on the addressinformation and a received address, the received address identifying atleast one memory cell in the cell array being accessed.
 2. The memorydevice of claim 1, wherein the control signal generation logic includesa comparator configured to compare the address information and thereceived, address, and the control signal generation logic is configuredto generate the control signal based on the comparison.
 3. The memorydevice of claim 2, wherein the comparator comprises: a row comparatorconfigured to compare the row address information with a received rowaddress represented by the received address; and a column comparatorconfigured to compare the column address information with a receivedcolumn address represented by the received address.
 4. The memory deviceof claim 3, wherein the row comparator includes a row address memoryunit, the w address memory unit configured to receive the row addressinformation from the storage device and store the row addressinformation; and the column comparator includes a column address memoryunit, the column address memory unit configured to receive the columnaddress information from the storage device and store the column addressinformation.
 5. The memory device of claim 4, wherein the storage deviceis a non-volatile memory device; and the row and column address memoryunits are volatile memory devices.
 6. The memory device of claim 5,wherein the volatile memory devices are content addressable memories. 7.The memory device of claim 2, wherein the comparator is configured togenerate a selection signal based on the comparison, the selectionsignal indicates whether a defective memory cell exists and identifies amemory group including the defective memory cell, and the control signalgeneration logic is configured to generate the control signal based onthe selection signal.
 8. The memory device of claim 7, wherein thecontrol signal generation logic further comprises: a code generatorconfigured to generate the control signal based on the selection signal.9. The memory device of claim 8, wherein the control signal includes abit for controlling operation of each selection unit in the data lineselection circuit.
 10. The memory device of claim 1, wherein the memorycell array includes first to nth memory cell groups, where n is greaterthan or equal to 2, each of the first to nth memory cell groupsassociated with first to nth data lines; and the data line selectioncircuit is configured to provide data paths between (i) the redundancydata line and the first to nth data lines and (ii) first to nthinput/output nodes.
 11. The memory device of claim 10, wherein the dataline selection circuit includes first to nth selection units, each ofthe first to nth selection units associated with a respective one thefirst to nth input/output nodes, each of the first to nth selectionunits having a first node associated with respective one of thefirst-nth data lines and having a second node associated with one of theredundancy data line and the first to nth data lines, each of the firstto nth selection units configured to provide to data path from one ofthe first and second nodes to the associated one of first to nthinput/output nodes based on the control signal.
 12. The memory device ofclaim 11, wherein each of the first to nth selection units itmultiplexer.
 13. The memory device of claim 11, wherein each of thefirst to nth input/output nodes is a DQ pad.
 14. The memory device ofclaim 11, wherein the control generation logic includes a comparatorconfigured to compare the address information and the received address,and the control signal generation logic is configured to generate thecontrol signal used on the comparison.
 15. The memory device of claim14, wherein the comparator is configured to generate a selection signalbased on the comparison, the selection signal indicates whether adefective memory cell exists and identifies a one of the first to nthmemory groups including the defective memory cell, and the controlsignal generation logic is configured to generate the control signalbased on the selection signal.
 16. The memory device of claim 15,wherein the control signal generation logic further comprises: a codegenerator configured to generate the control signal based on theselection signal, the control signal including a bit associated witheach of the first to nth selection units, each bit of the control signalindicating which of the first and second nodes of the associated one ofthe first to nth selection units to couple to the associated one of thefirst to nth input/output nodes.
 17. The memory device of claim 11,wherein the second node of the first to (n−1)th selection units isassociated with the data line for the second to nth memory cell groups;and the second node of the rah selection unit is associated with theredundancy data line; and the control signal generation logic isconfigured to generate a control signal such that if a detecteddefective memory cell is in the mth memory cell group, the first to mthselection units provide a data path including the second node, and the(m+1)th to nth selection units provide a data path including the firstnode.
 18. The memory device of claim 11, wherein the second node of thefirst to (n−1)th selection units is associated with the data line forthe first to (n−1)th memory cell groups; and the second node of thefirst selection unit is associated with the redundancy data line; andthe control signal generation logic is configured to generate a controlsignal such that if a detected defective memory cell is in the mthmemory cell group, the first to mth selection units provide a data pathincluding the second node, and the (m+1)th to nth selection unitsprovide a data path including the first node.
 19. The memory device ofclaim 10, wherein the control signal generation logic is configured togenerate the control signal such that the data paths provided by thedata line selection circuit do not include a one of the first to nthdata lines associated with a one of the first to nth memory cell groupsincluding a detected defective memory cell.
 20. The memory device ofclaim 10, wherein at least one the first to nth data lines is connectedto a sense amplifier arranged in a lengthwise direction of the memorycell array, and the redundancy data line is connected to a senseamplifier arranged in a widthwise direction of the memory cell array.21. The memory device of claim 1, wherein the first data line isconnected to a sense amplifier arranged in a lengthwise direction of thememory cell array, and the redundancy data lines is connected to a senseamplifier arranged in a widthwise direction of the memory cell array.22. The memory device of claim 10, wherein the storage device isconfigured to store address information such that one of the first tonth memory cell groups including a defective memory cell is replaced bythe redundancy memory cell group.
 23. The memory device of claim 1,wherein the storage device is configured to store address informationsuch that a defective memory cell is replaced by a single redundancymemory cell.
 24. The memory device of claim 23, wherein the selectioncontrol logic is configured to not replace non-defective memory cells ina column including the defective memory cell such that the non-defectivememory cells remain accessible.
 25. The memory device of claim 1,wherein the storage device is configured to store address informationsuch that a column of memory cells including a defective memory cell arereplaced by a column of redundancy memory cells.
 26. The memory deviceof claim 1, wherein the storage device is configured to store addressinformation such that only a portion of a column of memory cellsincluding a defective memory cell are replaced by a portion of a columnof redundancy memory cells.
 27. The memory device of claim 26, whereinthe selection control logic is configured to not replace non-defectivememory cells in a remaining portion of the column including thedefective memory cell such that the non-defective memory cells in theremaining portion remain accessible.
 28. The memory device of claim 1,wherein the first memory cell group includes at least one column ofinternal redundancy memory cells for replacing defective memory cells inthe first memory cell group.
 29. A memory device, comprising: a memorycell array having at least a first memory cell group and a redundancymemory cell group, the first memory cell group including a plurality offirst memory cells arranged in columns and rows, and the plurality offirst memory cells being associated with a first data line, and theredundancy memory cell group including a plurality of redundancy memorycells arranged in columns and rows, and the plurality of redundancymemory cells being associated with a redundancy data line; a data lineselection circuit; selection control logic configured to detect if adefective memory cell in the first memory group is being accessed, andconfigured to control the data line selection circuit to replace accessvia the first data line with access via the redundancy data line suchthat a portion of a column of the plurality of first memory cellsincluding the detected defective memory cell in the first group isreplaced with a portion of a column of the plurality of redundancymemory cells.
 30. The memory device of claim 29, wherein the portion ofthe column of the plurality of first memory cells includes anon-defective memory cell.
 31. The memory device of claim 29, whereinthe selection control logic is configured to not replace non-defectivememory cells in a remaining portion of the column including thedefective memory cell such that the non-defective memory cells in theremaining portion remain accessible.
 32. A memory device, comprising: amemory cell array having first to nth memory cell groups and aredundancy memory cell group, where n is greater than or equal to 2,each or the first to nth memory cell groups associated with first to nthdata lines, the first to nth memory cell groups including first to nthpluralities of memory cells arranged in columns and rows, and theredundancy memory cell group including a plurality of redundancy memorycells arranged in columns and rows, and the plurality of redundancymemory cells being associated with a redundancy data line; a data lineselection circuit; and selection control logic configured to detect if adefective memory cell in one of the first to nth memory groups is beingaccessed, and configured to control the data line selection circuit toreplace access via one of the first to nth data lines with access viathe redundancy data line such that the one of the first to nth memorycells groups including the detected defective memory cell is replacedwith the redundancy memory cell group.
 33. A memory device, comprising:a memory cell array having at least a first memory cell group and aredundancy memory cell group, the first memory cell group including aplurality of first memory cells arranged in columns and rows, and theplurality of first memory cells being associated with a first data line,and the redundancy memory cell group including a plurality of redundancymemory cells arranged in columns and rows, and the plurality ofredundancy memory cells being associated with a redundancy data line; adata line selection circuit; selection control logic configured todetect if a defective memory cell in the first memory group is beingaccessed, and configured to control the data line selection circuit toreplace access via the first data line with access via the redundancydata line such that a detected defective memory cell in the first groupis replaced with one of the plurality of redundancy memory cellsaccording to a desired replacement scheme, and the desired replacementscheme is a programmable feature of the selection control logic.
 34. Thememory device of claim 34, wherein the desired replacement scheme causesthe selection control logic to replace one of the first to nth memorycell groups including a defective memory cell with the redundancy memorycell group.
 35. The memory device of claim 34, wherein the desiredreplacement scheme causes the selection control logic to replace adefective memory cell with a single redundancy memory cell.
 36. Thememory device of claim 35, wherein the desired replacement scheme causesthe selection control logic to not replace non-defective memory cells ina column including the defective memory cell such that the non-defectivememory cells remain accessible.
 37. The memory device of claim 33,wherein the desired replacement scheme causes the selection controllogic to replace a column of memory cells including a defective memorycell with a column of redundancy memory cells.
 38. The memory device ofclaim 33, wherein the desired replacement scheme causes the selectioncontrol logic to replace only a portion of a column of memory cellsincluding a defective memory cell with a portion of a column ofredundancy memory cells.
 39. The memory device of claim 38, wherein thedesired replacement scheme causes the selection control logic to notreplace non-defective memory cells in a remaining portion of the columnincluding the defective memory cell such that the non-defective memorycells in the remaining portion remain accessible.
 40. The memory deviceof claim 33, wherein the selection control logic comprises: a storagedevice configured to be programmed with address information fordefective memory cells according to the desired replacement scheme, theaddress information including, row address information and columnaddress information identifying rows and columns in the first to nthmemory cell groups including defective memory cells, and control signalgeneration logic configured to generate a control signal for controllingthe data line selection circuit based on the address information and areceived address, the received address identifying at least one memorycell in the cell array being accessed.
 41. A method of replacingdefective memory cells in a memory cell array having at least a firstmemory cell group and a redundancy memory cell group, the first memorycell group including a plurality of first memory cells associated with afirst data line, and the redundancy memory cell group including aplurality of redundancy memory cells associated with a redundancy dataline, the method comprising: detecting if a defective memory cell in thefirst memory cell group is being accessed; and controlling a data lineselection circuit to replace access via, the first data line with accessvia the redundancy data line such that a detected defective memory cellin the first memory cell group is replaced with one of the plurality ofredundancy memory cells, the controlling including, storing, in astorage device, address information for defective memory cells, theaddress information including row address information and column addressinformation identifying rows and columns in the first memory cell groupincluding defective memory cells, and generating as control signal forcontrolling the data line selection circuit based on the addressinformation and a received address, the received address identifying atleast one memory cell in the cell array being accessed.
 42. A method ofreplacing defective memory cells in a memory cell array having at leasta first memory cell group and a redundancy memory cell group, the firstmemory cell group including a plurality of first memory cells arrangedin columns and rows, and the plurality of first memory cells beingassociated with a first data line, and the redundancy memory cell groupincluding a plurality of redundancy memory cells arranged in columns androws, and the plurality of redundancy memory cells being associated witha redundancy data line, the method comprising: detecting if a defectivememory cell in the first memory group is being accessed; andcontrolling, by a selection control logic, a data line selection circuitto replace access via the first data line with access via the redundancydata line such that a portion of a column of the plurality of firstmemory cells including the detected defective memory cell in the firstgroup is replaced with a portion of a column of the plurality ofredundancy memory cells.
 43. A method of replacing defective memorycells in a memory cell array having first to nth memory cell groups anda redundancy memory cell group, where n is greater than or equal to 2,each of the first to nth memory cell groups associated with first to nthdata lines, the first to nth memory cell groups including first to nthpluralities of memory cells arranged in columns and rows, and theredundancy memory cell group including a plurality of redundancy memorycells arranged in columns and rows, and the plurality of redundancymemory cells being associated with a redundancy data line, the methodcomprising: detecting if a defective memory cell in one of the first tonth memory groups is being accessed; and controlling, by a selectioncontrol logic, a data line selection circuit replace access via one thefirst to nth data lines with access via the redundancy data line suchthat the one of the first to nth memory cells groups including thedetected defective memory cell is replaced with the redundancy memorycell group.
 44. A method of replacing defective memory cells in asmemory cell array having at least a first memory cell group and aredundancy memory cell group, the lust memory cell group including aplurality of first memory cells arranged in columns and rows, and theplurality of first memory cells being associated with a first data line,and the redundancy memory cell group including a plurality of redundancymemory cells arranged in columns and rows, and the plurality ofredundancy memory cells being associated with a redundancy data line,the method comprising: detecting if a defective memory cell in the firstmemory group is being accessed; and controlling, by a selection controllogic, a data line selection circuit to replace access via the firstdata line with access via the redundancy data line such that a detecteddefective memory cell in the first group is replaced with one of theplurality of redundancy memory cells according to a desired replacementscheme, and the desired replacement scheme being a programmable featureof the selection control logic.